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    • 2. 发明公开
    • SIGNAL QUALITY EVALUATION DEVICE, SIGNAL QUALITY EVALUATION METHOD, AND PLAYBACK DEVICE
    • VORRICHTUNG ZURSIGNALQUALITÄTSBEURTEILUNG,VERFAHREN ZURSIGNALQUALITÄTSBEURTEILUNGUND WIEDERGABEVORRICHTUNG
    • EP2858070A1
    • 2015-04-08
    • EP13799823.3
    • 2013-04-26
    • Sony Corporation
    • SHIRAISHI, Junya
    • G11B20/18H03M13/41
    • H03M13/456G11B20/10268G11B20/10277G11B20/10305G11B20/10361G11B20/10379G11B20/1833H03M13/41H03M13/6343
    • Provided is a signal quality evaluation apparatus, including an error pattern detection unit to which binarized data obtained by performing a PRML decoding process on a reproduced signal of bit information by partial response equalization and maximum likelihood decoding is input, the error pattern detection unit configured to detect at least one specific error pattern that is a bit pattern that is longer than a constraint length of the PRML decoding process, a metric difference calculation unit configured to calculate a metric difference of the at least one specific error pattern that has been detected by the error pattern detection unit, and an index value generation unit configured to generate an index value of a reproduced signal quality by using a distribution of the metric difference obtained by the metric difference calculation unit.
    • 提供了一种信号质量评估装置,其包括错误模式检测单元,其中通过对通过部分响应均衡和最大似然解码的比特信息的再现信号执行PRML解码处理获得的二进制数据被输入,所述错误模式检测单元被配置为 检测作为比PRML解码处理的约束长度更长的位模式的至少一个特定错误模式;度量差计算单元,被配置为计算由所述PRML解码处理检测到的所述至少一个特定错误模式的度量差异 误差模式检测单元和指标值生成单元,被配置为通过使用由度量差计算单元获得的度量差的分布来生成再现信号质量的指标值。
    • 3. 发明公开
    • Procédé et dispositif de decodage à l'aide de codes correcteurs d'erreurs
    • 对于具有误差校正码的辅助解码方法和装置
    • EP1909396A2
    • 2008-04-09
    • EP07117639.0
    • 2007-10-01
    • FRANCE TELECOM
    • POIRRIER, Julien, ILE DE FRANCE FRANCE TELECOMJOINDOT, Michel, ILE DE FRANCE FRANCE TELECOM
    • H03M13/35
    • H03M13/353H03M13/37H03M13/456
    • L'invention concerne un procédé de décodage d'un signal décidé reçu d'un circuit de décision en un signal décodé, ledit procédé comprenant:
      - une étape de détection d'un mot de N éléments binaires dans ledit signal décidé reçu, destinée à fournir un mot détecté,
      - une étape de sélection d'un mot admissible de N éléments binaires dans un dictionnaire du code correcteur d'erreurs utilisé à l'encodage selon un critère de plus courte distance entre ledit mot détecté et ledit mot admissible sélectionné, et
      - une étape de décodage d'un mot de L éléments binaires d'information constituant ledit signal décodé à partir dudit mot admissible sélectionné.
      Selon l'invention, la distance mise en oeuvre dans l'étape de sélection prend en compte une fiabilité relative de 2 k séquences de K éléments binaires, 0
    • 该方法包括检测在所接收的信号决定(VD)N二进制元素(VND)的一个字。 N个二进制元素的容许字(W Na)的中的在编码实施错误校正码,gemäß字典被选择为检测到的字和所选择的容许字之间的短距离标准。 构成解码信号(DL)L-二进制元素的字是从所选择的允许的字,其中,所述距离认为k个二元元件的两个功率k个序列相对可靠性提供位于其中,k 0和N独立权利要求因此被包括之间 为以下几点:(1)一个决定信号解码器包括检测单元(2)的解码装置,包括解码器(3)一种接收机,包括一个决定电路(4)的计算机程序产品,其包括一组指令,用于执行一种方法的 的信号进行解码来决定。
    • 5. 发明公开
    • Soft decision decoding of error correcting block codes using the fast Hadamard transform
    • 由快速阿达玛的软判决纠错块码解码变换
    • EP1465351A2
    • 2004-10-06
    • EP04007728.1
    • 2004-03-30
    • Samsung Electronics Co., Ltd.
    • Park, Sung-EunKim, Jae-YoelPark, Seong-IIIKim, Young-KyunLee, Hyeon-Woo
    • H03M13/05H03M13/45
    • H03M13/136H03M13/45H03M13/456
    • The application proposes an apparatus and a method for maximazing decoding performance by performing the soft decision decoding utilizing the inverse fast Hadamard transform (IFHT) even for block codes where the generator matrix does not include a basis of a Walsh code. In the apparatus, symbol position information for relocating each reception symbol is determined utilizing the block code generator matrix information having k rows and n columns and an IFHT size information for performing an IFHT for the reception symbols, each reception symbol is relocated as an input of an IFHT unit according to the determined symbol position information, the relocated symbols are input and the IFHT is performed for the symbols; and a codeword of the block code, which has a maximum correlation value from among result values obtained by performing the IFHT, is output as a decoding signal.
    • 该申请提出了几乎Hadamard变换的装置和用于通过执行软判决解码利用即使对于块码,其中该生成矩阵不包括的沃尔什码的基础的倒数(IFHT)maximazing解码性能的方法。 在重定位的每个接收符号的装置中,符号位置信息确定的开采利用具有用于在IFHT执行对接收码元k行和n列和IFHT尺寸信息块代码生成器矩阵的信息,每个接收符号被重新定位,以输入 到IFHT单元gemäß到确定性开采符号的位置信息,重新定位的符号被输入和IFHT执行用于符号; 和块代码,从通过执行IFHT获得的结果值中具有最大相关值的码字,是作为解码信号输出。
    • 10. 发明公开
    • BRUTE FORCE CHANNEL DECODING
    • 蛮力,KANALDEKODIERUNG
    • EP2174423A1
    • 2010-04-14
    • EP08775848.8
    • 2008-07-02
    • Cambridge Silicon Radio Limited
    • CHAPPAZ, David, F.
    • H03M13/45H03M13/23
    • H03M13/23H03M13/456H03M13/653
    • An embodiment of the present invention provides that pre-calculated code words corresponding to possible input bit sequences are stored in a UE, and then a similarity matching operation performed between a received coded bit sequence and the stored code words can be performed to identify that code word which most closely matches to the received sequence. Because the stored code words are associated with the original input bit sequences which produced those code words, by identifying the most closely correlating code word to a received coded sequence, then the input sequence which generated the matching code word can also be identified, and output as the decoder output. In this way, a more efficient decoding operation is obtained as decoding is no longer dependent upon a Viterbi decoding operation and moreover it is no longer necessary to implement a Viterbi decoder, instead merely requiring storage for the pre-calculated code words. In the specific case of the HS-SCCH Part 1 a code word table comprising 256 40 bit is required. This is significantly easier to implement and is more efficient in terms of chip area, than providing a dedicated Viterbi decoder to decode the HS-SCCH Part 1 channel.