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1. 发明公开

EP2093888A3 Soft-output Viterbi detection using a Radix-n trellis 失效转让
标题翻译：维特比检测与使用基数-N格软判决
公开(公告)号：EP2093888A3
公开(公告)日：2012-04-25
申请号：EP09162284.5
申请日：2005-11-14
申请人： Agere Systems, Inc.
发明人： Ashley, Jonathan James , Fitzpatrick, Kelly Knudson , Haratsch, Erich Franz
IPC分类号： H03M13/41
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

2. 发明公开

EP2083520A3 Method and apparatus for map detection with reduced complexity 审中-公开
标题翻译：为最大后验概率检测具有降低的复杂性的方法和装置
公开(公告)号：EP2083520A3
公开(公告)日：2009-08-19
申请号：EP09151154.3
申请日：2009-01-22
申请人： Agere Systems, Inc.
发明人： Fitzpatrick, Kelly K. , Haratsch, Erich F.
IPC分类号： H03M13/39 , H04L1/00
CPC分类号： G11B5/09 , H03M13/3905 , H03M13/395 , H03M13/6343 , H03M13/6502 , H04L1/0055 , H04L1/0066
摘要： Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.

3. 发明公开

EP2083520A2 Method and apparatus for map detection with reduced complexity 审中-公开
标题翻译：降低复杂度的地图检测方法和装置
公开(公告)号：EP2083520A2
公开(公告)日：2009-07-29
申请号：EP09151154.3
申请日：2009-01-22
申请人： Agere Systems, Inc.
发明人： Fitzpatrick, Kelly K. , Haratsch, Erich F.
IPC分类号： H03M13/39 , H04L1/00
CPC分类号： G11B5/09 , H03M13/3905 , H03M13/395 , H03M13/6343 , H03M13/6502 , H04L1/0055 , H04L1/0066
摘要： Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.
摘要翻译：提供了用于高速，低功率，高性能信道检测的方法和装置。提供一个软输出通道检测器，以1 / N的速率工作，并检测每个1 / N速率时钟周期的N位。信道检测器包括并行操作的多个MAP检测器，其中每个MAP检测器每个1 / N速率时钟周期产生N / D对数似然比值，并且其中多个MAP检测器中的至少一个约束每个比特。对数似然比值可以合并以形成输出序列。还提供单个MAP检测器，其包括用于计算正向状态度量的正向检测器; 用于计算反向状态量度的后向检测器; 以及电流分支检测器，用于计算电流分支量度，其中正向检测器，反向检测器和当前分支检测器中的至少两个采用不同的格子结构。

4. 发明公开

EP2011239A2 RADIX-4 VITERBI DECODING 审中-公开
标题翻译：基数-4维特比解码
公开(公告)号：EP2011239A2
公开(公告)日：2009-01-07
申请号：EP07761495.6
申请日：2007-04-27
申请人： QUALCOMM Incorporated
发明人： SHIH, Garret Webster
IPC分类号： H03M13/41
CPC分类号： H03M13/4107 , H03M13/395 , H03M13/3961 , H03M13/4176
摘要： Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals. Such techniques include radix-4 two stage decoding. The encoded signals may include soft decision signals. A Viterbi decoder may include a branch metric generator, a trellis interconnect, an add-compare element, a path metric memory, and a traceback element. The add-compare element may include a plurality of add- compare-select units that each select two trace bits per clock cycle. The traceback element may write, decode, and trace stored trace bits to decode the encoded signal.

5. 发明公开

EP1394953A2 LOG-MAP processor for higher radix trellis 审中-公开
标题翻译： LOG-MAP处理器，用于更高基数网格
公开(公告)号：EP1394953A2
公开(公告)日：2004-03-03
申请号：EP03255069.1
申请日：2003-08-14
申请人： LUCENT TECHNOLOGIES INC.
发明人： Bickerstaff, Mark Andrew , Davis, Linda Mary
IPC分类号： H03M13/29
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/3922 , H03M13/3927 , H03M13/395
摘要： A Log Map processor that processes information in accordance with the Log MAP algorithm using an N-state Radix-K trellis where K is an integer equal to 4 or greater and N is an integer equal to 2 or greater, wherein K branches enter and leave each trellis state. The Log Map processor comprises branch and path metric calculators designed with LogSum operators. The LogSum operators used and Add-Compare-Select architecture that is based on an approximation of the Jacobian definition of the LogSum operation. The Log Map processor is thus able to process relatively more information per unit time.
摘要翻译：日志映射处理器，其根据LogMAP算法使用N状态基数K格栅处理信息，其中K是等于或大于4的整数，并且N是等于2或更大的整数，其中K个分支进入和离开每个网格状态。 Log Map处理器包含使用LogSum操作符设计的分支和路径度量计算器。使用LogSum运算符和Add-Compare-Select体系结构，该体系结构基于LogSum操作的雅可比行列式的近似值。日志图处理器因此能够处理每单位时间相对更多的信息。

6. 发明公开

EP0138598A3 Error correction apparatus using a viterbi decoder 有权
标题翻译：错误修正装置使用VITERBI解码器
公开(公告)号：EP0138598A3
公开(公告)日：1988-03-16
申请号：EP84307011
申请日：1984-10-12
申请人： NEC CORPORATION
发明人： Otani, Susumu
IPC分类号： H03M13/12
CPC分类号： H03M13/395 , H03M13/41
摘要： Received, convolutionally coded bits are grouped and applied to a branch metric calculator and an adder to provide a plurality (sixteen) of sums of branch metrics over branches defining two depths of a Viterby trellis diagram corresponding to the convolutional code. Such sums, of the form Z 11 +Z 11 , Z 31 + Zi etc. where the two components of each sum pertain to successive time slots and the index values specify the path branches, are applied to terminals (31-34,41-44) forming first inputs to sixteen adders (eight shown, 301-304, 401-404) whose other inputs receive appropriate ones of four stored path metrics (M l - M 4 ). The adders all operate in parallel and the stored metrics are updated over two depths of the trellis diagram by an arrangement of comparators and selectors effecting two levels of comparison and selection. For example, in the firstlevel a comparator (305) compares the sum from one pair of adders (301, 302) and controls both a selector (307) for that pair of adders and a selector (407) for another pair of adders (401,402). In the second level comparators (309, 409) and corresponding selectors (310, 410) select between outputs of pairs of first level selectors. The control signals from all the comparators indicating the determinations made thereby are coupled to a path memory (101) indicating the paths of the selected values and hence the decoded output bits corresponding to the servicing paths.

7. 发明公开

EP2940876A1 MULTIMODE DECODER IMPLEMENTATION METHOD AND DEVICE 审中-公开
标题翻译：实施多功能解码器
公开(公告)号：EP2940876A1
公开(公告)日：2015-11-04
申请号：EP13869737.0
申请日：2013-10-25
申请人： ZTE Corporation
发明人： DU, Jinzhou
IPC分类号： H03M13/23 , H04L27/06
CPC分类号： H03M13/6525 , H03M13/2957 , H03M13/3905 , H03M13/395 , H03M13/6519 , H03M13/6544 , H04L1/005 , H04L1/0055 , H04L1/0066 , H04L1/0071
摘要： Disclosed are a multimode decoder method and device. The method includes: interleaving pre-stored to-be-decoded data to obtain an interleaving address; and based on the interleaving address, using a Radix-4 algorithm architecture, multiplexing a set of MAP decoding units under different standards, and in a parallel processing method, performing MAP iterative decoding processing on the to-be-decoded data according to standard types.
摘要翻译：公开了一种多模式解码器方法和装置。该方法包括：交织预先存储的解码数据以获得交织地址; 并且基于交织地址，使用基数4算法架构，在不同标准下复用一组MAP解码单元，并且以并行处理方法，根据标准类型对待解码的数据执行MAP迭代解码处理。

8. 发明授权

EP1154578B1 High-speed turbo decoder 有权
标题翻译：快速Turbo解码器
公开(公告)号：EP1154578B1
公开(公告)日：2015-01-21
申请号：EP01111572.2
申请日：2001-05-11
申请人： NEC Corporation
发明人： Maru, Tsuguo
IPC分类号： H03M13/29
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/3922 , H03M13/395 , H03M13/616

9. 发明公开

EP2598995A4 ACCESSING MEMORY FOR DATA DECODING 审中-公开
标题翻译：访问内存数据解码
公开(公告)号：EP2598995A4
公开(公告)日：2014-02-19
申请号：EP11812852
申请日：2011-07-26
申请人： MEDIATEK SINGAPORE PTE LTD
发明人： FISHER-JEFFES TIMOTHY PERRIN
IPC分类号： H03M13/27 , H03M13/29 , H03M13/39
CPC分类号： H04L1/0066 , H03M13/2775 , H03M13/2957 , H03M13/395 , H03M13/6505 , H03M13/6561 , H03M13/6566 , H04L1/0043 , H04L1/0052

10. 发明公开

EP2598995A2 ACCESSING MEMORY FOR DATA DECODING 审中-公开
标题翻译：访问内存数据解码
公开(公告)号：EP2598995A2
公开(公告)日：2013-06-05
申请号：EP11812852.9
申请日：2011-07-26
申请人： MediaTek Singapore Pte Ltd.
发明人： FISHER-JEFFES, Timothy Perrin
IPC分类号： G06F12/00 , G06F11/10
CPC分类号： H04L1/0066 , H03M13/2775 , H03M13/2957 , H03M13/395 , H03M13/6505 , H03M13/6561 , H03M13/6566 , H04L1/0043 , H04L1/0052
摘要： A method comprises receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements. The method also comprises identifying each of the unique memory addresses as being included in one group of a plurality of address groups. Each address group substantially includes an equivalent number of unique addresses. The method also comprises, in parallel, accessing at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed.

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