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    • 1. 发明公开
    • SIGNALVERARBEITUNGSEINRICHTUNG UND STEUEREINRICHTUNG
    • 信号处理装置和控制装置
    • EP3298689A1
    • 2018-03-28
    • EP16715294.1
    • 2016-04-08
    • Robert Bosch GmbH
    • BRUCKHAUS, Tim
    • H03H1/02H03H7/42
    • H03H7/06G05F3/08H02P6/00H03H1/02H03H7/427
    • The present invention discloses a signal processing device for processing a differential signal from a sensor at a prescribed signal frequency, having a positive signal input (5-1), which is couplable to a positive sensor output of the sensor, and a negative signal input (6-1), which is couplable to a negative sensor output of the sensor, having a positive signal output (7-1) and having a negative signal output (8-1), having a first frequency-dependent resistance (C1H) between the positive signal input (5-1) and the positive signal output (7-1) and having a second frequency-dependent resistance (C1L) between the negative signal input (6-1) and the negative signal output (8-1), wherein the first and second frequency-dependent resistances (C1H, C1L) are designed to allow electrical signals at the prescribed signal frequency to pass in approximately unattenuated fashion, having a first voltage divider (11), which is arranged at least in part in parallel with the first frequency-dependent resistance (C1H) and is designed to divide a voltage between the positive signal input (5-1) and the positive signal output (7-1) using a prescribed ratio, having a second voltage divider (12), which is arranged at least in part in parallel with the second frequency-dependent resistance (C1L) and is designed to divide a voltage between the negative signal input (6-1) and the negative signal output (8-1) using a prescribed ratio. Further, the present invention discloses a control device for an electric machine.
    • 5. 发明公开
    • COMPLEX LAMINATED CHIP ELEMENT
    • 复合层压芯片元件
    • EP1654763A1
    • 2006-05-10
    • EP04774129.3
    • 2004-07-15
    • Innochips Technology Co., Ltd.Park, In-KilHwang, Soon-HaKim, Duk-Hee
    • Park, In-KilHwang, Soon-HaKim, Duk-Hee
    • H01L27/02
    • H01G4/40H01C1/148H01C7/008H01C7/18H01C13/02H01F17/0006H01F27/40H01F2017/0026H01G4/232H01G4/35H03H1/02H03H2001/0014H03H2001/0085H03H2001/0092
    • The present invention relates to a laminated chip element which can be manufactured to have desired electric properties by combining various elements in accordance with the desired objectives. More p articularly, t he present invention relates to a laminated chip element which has superior high frequency properties and can be manufactured to control capacitance and/or inductance of the laminated chip element to a desired value. There is provided a laminated chip element, comprising at least one first sheet on which first and second conductive patterns are formed, the first and second conductive patterns being spaced apart from each other in a direction of both ends of the first sheet; and at least one second sheet on which a third conductive pattern is formed, the third conductive pattern being formed in a transverse direction of both the ends of the first sheet; wherein one ends of the first and second conductive patterns are connected to first and second external terminals, respectively, at least one end of the third conductive pattern is connected to a third external terminal, and the first and second sheets are laminated. There is also provided a laminated chip element, comprising: at least one first sheet on which a first conductive pattern is formed, the first conductive pattern consisting of first to third portions, the first and second portions being spaced apart from each other in a direction of both ends of the first sheet, the second portion connecting the first and second portions to each other to have a predetermined inductance; and at least one second sheet on which a second conductive pattern is formed in a transverse direction of both the ends of the first sheet; wherein the first and second portions are connected to first and second external terminals, respectively, at least one ends of the second conductive pattern is connected to a third external terminal, and the first and second sheets are laminated.
    • 10. 发明公开
    • Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
    • 用于校准集成电路的可调电容的时间常数依赖于电容校准电路
    • EP1962421A1
    • 2008-08-27
    • EP07425100.0
    • 2007-02-23
    • STMicroelectronics S.r.l.
    • Confalonieri, PierangeloMartignone, RiccardoZamprogno, Marco
    • H03H1/02H03H7/01
    • H03H1/02H03H7/0153H03H2210/021H03H2210/025H03H2210/036H03H2210/043
    • A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitor (C var (REG_BUS)) and including a calibration loop (RC_DEL, DFF, TG_SAR) comprising:
      - a controllable capacitance unit (RC_DEL) suitable to receive a control signal (SAR_BUS) and including at least one array of switched capacitors (C_AR1, CAR_2), that can be activated by means of the control signal (SAR_BUS), the unit (RC_DEL) being such as to output a first signal (OUT_DEL) characterized by a parameter depending on the amount of capacitance of the array (C_AR1, CAR_2) activated by the control signal (SAR_BUS);
      - a comparison unit (DFF) suitable to receive said first signal (OUT_DEL) to assess whether said parameter meets a preset condition and to output a comparison signal (OUT_DFF) representative of the assessment result;
      - a control and timing logic unit (TG_SAR) suitable to receive the comparison signal (OUT_DFF) to change this control signal (SAR_BUS) based on said comparison signal (OUT_DFF),

      characterized in that
      said first signal (OUT_DEL) is a logic signal and said parameter is a time parameter of said first signal.
    • 用于校准(在具有时间常数取决于所述可调电容的电路(31)的可调节的电容(C VAR(REG_BUS))的校准电路(30),所述校准电路(30)被检查,以输出一个校准信号REG_BUS )携带信息用于校准所述电容器(C VAR(REG_BUS)),并且包括一个校准循环(RC_DEL,DFF,TG_SAR),包括: - 一个可控电容单元(RC_DEL)适合于接收控制信号(SAR_BUS)和包括至少一个 开关电容器(C_AR1,CAR_2)的阵列也可以由控制信号(SAR_BUS),单元(RC_DEL)的方式来激活正被检查,以输出由参数为特征的第一信号(OUT_DEL)上的电容的量根据 由控制信号(SAR_BUS)激活阵列(C_AR1,CAR_2)的; - 一个比较单元(DFF),其适于接收所述第一信号(OUT_DEL)评估是否所述参数是否满足预设条件,并输出比较信号(OUT_DFF)代表评估结果的一个; - 控制和定时逻辑单元(TG_SAR)适合于基于所述比较信号(OUT_DFF)接收比较信号(OUT_DFF)来改变该控制信号(SAR_BUS)表示,在这特点第一信号(OUT_DEL)是一个逻辑信号,并且 所述参数是所述第一信号的时间参数。