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1. 发明授权

EP1544913B1 Semiconductor device and method of manufacturing thereof 有权
公开(公告)号：EP1544913B1
公开(公告)日：2015-09-02
申请号：EP04029836.6
申请日：2004-12-16
申请人： Seiko Epson Corporation
发明人： Ito, Haruki
IPC分类号： H01L23/31
CPC分类号： H01L23/5226 , H01L23/293 , H01L23/3114 , H01L23/3192 , H01L23/49816 , H01L23/5329 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/17 , H01L2224/02125 , H01L2224/02126 , H01L2224/02331 , H01L2224/0236 , H01L2224/02373 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/02381 , H01L2224/024 , H01L2224/11334 , H01L2224/1146 , H01L2224/13014 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/14131 , H01L2224/16225 , H01L2224/16227 , H01L2224/94 , H01L2924/0002 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/013 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/186 , H01L2924/3512 , H01L2924/00 , H01L2224/11
摘要： The object of the invention disclosed here is the provision of a semiconductor device, which can correspond to a large size chip and be provided with many external terminals with fine wiring with high reliable connection. A semiconductor device (1) comprises a semiconductor element (2) including a plurality of electrodes (9); a single or a plurality of resin layers, a plurality of wirings (4) electrically connected to the electrode (9), and a plurality of external terminals (7) electrically connected to the wirings (4). A part of or all of the plurality of wirings (4) comprises a first wiring (4a) directed to the center (10) of the semiconductor element (2) from a portion coupled to the electrodes (9); and a second wiring (4b) which is directed to an outer area from the center (10) of the semiconductor element (2) and coupled to the external terminals (7). At least one resin layer is formed between the first wiring (4a) and the second wiring (4b).

3. 发明公开

EP3091573A2 SEMICONDUCTOR CHIP PACKAGE ASSEMBLY WITH IMPROVED HEAT DISSIPATION PERFORMANCE 审中-公开
标题翻译： HALBLEITER-CHIPPACKUNGSANORDNUNG MIT VERBESSERTERWÄRMEABLEITUNGSLEISTUNG
公开(公告)号：EP3091573A2
公开(公告)日：2016-11-09
申请号：EP16161852.5
申请日：2016-03-23
申请人： MediaTek, Inc
发明人： HSIAO, Ching-Wen , LIN, Tzu-Hung , PENG, I-Hsuan , HSIEH, Tung-Hsien , CHANG, Sheng-Ming
IPC分类号： H01L25/16 , H01L25/10 , H01L23/538 , H01L23/34 , H01L23/50
CPC分类号： H01L23/3675 , H01L23/3114 , H01L23/3121 , H01L23/3677 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L23/50 , H01L23/5389 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/02373 , H01L2224/0401 , H01L2224/04105 , H01L2224/05572 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/92125 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06589 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/00012 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor chip package assembly (1) includes a package substrate (200) having a chip mounting surface (200a); a plurality of solder pads (212) disposed on the chip mounting surface; a first dummy pad (211) and a second dummy pad (211) spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask (202) on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package (100) mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls (250) on respective said solder pads (212); a discrete device (150)having a first terminal (151) and a second terminal (152) disposed between the chip package and the package substrate; a first solder (154) connecting the first terminal with the first dummy pad (211) and the chip package (100); and a second solder (154) connecting the second terminal (152) with the second dummy pad (211) and the chip package (100).
摘要翻译：半导体芯片封装组件（1）包括具有芯片安装表面（200a）的封装衬底（200）; 设置在所述芯片安装表面上的多个焊盘（212）; 与设置在芯片安装表面上的第一虚拟焊盘间隔开的第一虚拟焊盘（211）和第二虚拟焊盘（211）; 在芯片安装表面上的焊接掩模（202），并且部分地覆盖焊盘，第一虚拟焊盘和第二虚拟焊盘; 芯片封装（100），其安装在所述芯片安装表面上并且通过在所述焊盘（212）上的多个焊球（250）电连接到所述封装基板; 具有设置在所述芯片封装和所述封装基板之间的第一端子（151）和第二端子（152）的分立器件（150）将第一端子与第一虚拟焊盘（211）和芯片封装（100）连接的第一焊料（154）; 以及将第二端子（152）与第二虚拟焊盘（211）和芯片封装（100）连接的第二焊料（154）。

4. 发明公开

EP3059762A2 WAFER-LEVEL PACKAGE HAVING MULTIPLE DIES ARRANGED IN SIDE-BY-SIDE FASHION AND ASSOCIATED YIELD IMPROVEMENT METHOD 有权
标题翻译：带有多个SIDE并排布置CHIPS和相关收入增长的加工晶片层包装
公开(公告)号：EP3059762A2
公开(公告)日：2016-08-24
申请号：EP16155928.1
申请日：2016-02-16
申请人： MediaTek, Inc
发明人： CHEN, Yi-Hung , LIU, Yuan-Chin
IPC分类号： H01L25/065 , H01L25/00 , H01L23/538 , H01L23/00
CPC分类号： H01L24/02 , H01L23/538 , H01L23/5384 , H01L25/0655 , H01L25/50 , H01L2224/02371 , H01L2224/02373 , H01L2224/02379 , H01L2224/0401 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
摘要： A wafer-level package includes a plurality of dies (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1502, 1504_1-1504_2, 1602, 1604_1-1604_4) and a plurality of connection paths. The dies include at least a first die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4) and a second die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4). The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output pads arranged on the first side of the first die to input/output pads arranged on the first side of the second die, wherein adjacent input/output pads on the first side of the first die are connected to adjacent input/output pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out package or a chip on wafer on substrate package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.
摘要翻译：一种晶片级封装包括这种有多个（602_1-602_2，702_1-702_4，802_1-802_2，902_1-902_4，1002_1-1002_3，1102_1-1102_2，1202_1-1202_2，1502，1504_1-1504_2，1602，1604_1-1604_4 ）和连接路径复数。如此包括至少第一，第（602_1-602_2，702_1-702_4，802_1-802_2，902_1-902_4，1002_1-1002_3，1102_1-1102_2，1202_1-1202_2，1504_1-1504_2，1604_1-1604_4）和第二那（ 602_1-602_2，702_1-702_4，802_1-802_2，902_1-902_4，1002_1-1002_3，1102_1-1102_2，1202_1-1202_2，1504_1-1504_2，1604_1-1604_4）。的这个布置成并排侧的方式，与所述第一管芯的第一侧邻近于所述第二那的第一侧。连接路径连接设置在所述第一，到输入/输出焊盘布置在第二其中worin在第一的第一侧被连接到相邻的相邻的输入/输出焊盘的第一侧的第一侧的输入/输出焊盘经由路径仅单个层上的第二连接的所述第一侧的输入/输出焊盘。对于实施例，其中第一个是相同的第二对。对于另一实施例中，晶片级封装是一个集成的扇出包或上包晶片基底的芯片。对于又一实施例中，它被组装在晶片级封装执行网络切换功能。

5. 发明公开

EP3220410A4 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME 审中-公开
公开(公告)号：EP3220410A4
公开(公告)日：2018-07-18
申请号：EP14890461
申请日：2014-11-13
申请人： RENESAS ELECTRONICS CORP
发明人： MAEKAWA KAZUYOSHI , KAWANO YUICHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L24/02 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/02181 , H01L2224/02185 , H01L2224/0219 , H01L2224/02331 , H01L2224/0235 , H01L2224/02373 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03466 , H01L2224/0347 , H01L2224/035 , H01L2224/03614 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05008 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/05176 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05566 , H01L2224/05567 , H01L2224/05664 , H01L2224/2919 , H01L2224/32225 , H01L2224/4502 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/48465 , H01L2224/48664 , H01L2224/48864 , H01L2224/73265 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01046 , H01L2924/04941 , H01L2924/07025 , H01L2924/10253 , H01L2924/1306 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/01008
摘要： A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

6. 发明公开

EP3220410A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP3220410A1
公开(公告)日：2017-09-20
申请号：EP14890461.8
申请日：2014-11-13
申请人： Renesas Electronics Corporation
发明人： MAEKAWA, Kazuyoshi , KAWANO, Yuichi
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L24/02 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/02181 , H01L2224/02185 , H01L2224/0219 , H01L2224/02331 , H01L2224/0235 , H01L2224/02373 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03466 , H01L2224/0347 , H01L2224/035 , H01L2224/03614 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05008 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/05176 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05566 , H01L2224/05567 , H01L2224/05664 , H01L2224/2919 , H01L2224/32225 , H01L2224/4502 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/48465 , H01L2224/48664 , H01L2224/48864 , H01L2224/73265 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01046 , H01L2924/04941 , H01L2924/07025 , H01L2924/10253 , H01L2924/1306 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/01008
摘要： A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.
摘要翻译：一种半导体器件包括：形成在多个布线层的最上层中的焊盘电极9a; 在焊盘电极9a上具有开口部11a的基底绝缘膜11，形成在基底绝缘膜11上的基底金属膜UM，形成在基底金属膜UM上的再分布线RM; 以及形成为覆盖再分布线RM的上表面和侧表面的帽金属膜CM。另外，在再分布线RM之外的区域中，由与再分布线RM不同的材料制成的基底金属膜UM和由与再分布线RM不同的材料制成的盖金属膜CM形成在盖之间形成在再分布线RM和基底绝缘膜11的侧面上的金属膜CM以及基底金属膜UM和盖金属膜CM在再分布线RM外侧的区域中彼此直接接触。

7. 发明公开

EP3091573A3 SEMICONDUCTOR CHIP PACKAGE ASSEMBLY WITH IMPROVED HEAT DISSIPATION PERFORMANCE 审中-公开
标题翻译：具有更好的散热功率半导体芯片封装布局
公开(公告)号：EP3091573A3
公开(公告)日：2017-02-22
申请号：EP16161852.5
申请日：2016-03-23
申请人： MediaTek, Inc
发明人： HSIAO, Ching-Wen , LIN, Tzu-Hung , PENG, I-Hsuan , HSIEH, Tung-Hsien , CHANG, Sheng-Ming
IPC分类号： H01L25/16 , H01L25/10 , H01L23/538 , H01L23/34 , H01L23/50
CPC分类号： H01L23/3675 , H01L23/3114 , H01L23/3121 , H01L23/3677 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L23/50 , H01L23/5389 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/02373 , H01L2224/0401 , H01L2224/04105 , H01L2224/05572 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/92125 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06589 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/00012 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor chip package assembly (1) includes a package substrate (200) having a chip mounting surface (200a); a plurality of solder pads (212) disposed on the chip mounting surface; a first dummy pad (211) and a second dummy pad (211) spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask (202) on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package (100) mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls (250) on respective said solder pads (212); a discrete device (150)having a first terminal (151) and a second terminal (152) disposed between the chip package and the package substrate; a first solder (154) connecting the first terminal with the first dummy pad (211) and the chip package (100); and a second solder (154) connecting the second terminal (152) with the second dummy pad (211) and the chip package (100).

8. 发明公开

EP1544913A2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：EP1544913A2
公开(公告)日：2005-06-22
申请号：EP04029836.6
申请日：2004-12-16
申请人： SEIKO EPSON CORPORATION
发明人： Ito, Haruki
IPC分类号： H01L23/31
CPC分类号： H01L23/5226 , H01L23/293 , H01L23/3114 , H01L23/3192 , H01L23/49816 , H01L23/5329 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/17 , H01L2224/02125 , H01L2224/02126 , H01L2224/02331 , H01L2224/0236 , H01L2224/02373 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/02381 , H01L2224/024 , H01L2224/11334 , H01L2224/1146 , H01L2224/13014 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/14131 , H01L2224/16225 , H01L2224/16227 , H01L2224/94 , H01L2924/0002 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/013 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/186 , H01L2924/3512 , H01L2924/00 , H01L2224/11
摘要： The object of the invention disclosed here is the provision of a semiconductor device, which can correspond to a large size chip and be provided with many external terminals with fine wiring with high reliable connection. A semiconductor device (1) comprises a semiconductor element (2) including a plurality of electrodes (9); a single or a plurality of resin layers, a plurality of wirings (4) electrically connected to the electrode (9), and a plurality of external terminals (7) electrically connected to the wirings (4). A part of or all of the plurality of wirings (4) comprises a first wiring (4a) directed to the center (10) of the semiconductor element (2) from a portion coupled to the electrodes (9); and a second wiring (4b) which is directed to an outer area from the center (10) of the semiconductor element (2) and coupled to the external terminals (7). At least one resin layer is formed between the first wiring (4a) and the second wiring (4b).
摘要翻译：这里公开的本发明的目的是提供一种半导体器件，该半导体器件可以对应于大尺寸芯片并且具有许多具有高可靠连接的精细布线的外部端子。半导体装置（1）包括：具有多个电极（9）的半导体元件（2）; 一个或多个树脂层，电连接到电极（9）的多个布线（4），以及电连接到布线（4）的多个外部端子（7）。多个布线（4）的一部分或全部包括从与电极（9）连接的部分朝向半导体元件（2）的中心（10）的第一布线（4a），以及从半导体元件（2）的中心（10）朝向外部区域并耦合到外部端子（7）的第二布线（4b）。在第一布线（4a）和第二布线（4b）之间形成至少一个树脂层。

9. 发明公开

EP3059762A3 WAFER-LEVEL PACKAGE HAVING MULTIPLE DIES ARRANGED IN SIDE-BY-SIDE FASHION AND ASSOCIATED YIELD IMPROVEMENT METHOD 有权
标题翻译：带有多个SIDE并排布置CHIPS和相关收入增长的加工晶片层包装
公开(公告)号：EP3059762A3
公开(公告)日：2016-11-09
申请号：EP16155928.1
申请日：2016-02-16
申请人： MediaTek, Inc
发明人： CHEN, Yi-Hung , LIU, Yuan-Chin
IPC分类号： H01L25/065 , H01L25/00 , H01L23/538 , H01L23/00
CPC分类号： H01L24/02 , H01L23/538 , H01L23/5384 , H01L25/0655 , H01L25/50 , H01L2224/02371 , H01L2224/02373 , H01L2224/02379 , H01L2224/0401 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
摘要： A wafer-level package includes a plurality of dies (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1502, 1504_1-1504_2, 1602, 1604_1-1604_4) and a plurality of connection paths. The dies include at least a first die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4) and a second die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4). The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output pads arranged on the first side of the first die to input/output pads arranged on the first side of the second die, wherein adjacent input/output pads on the first side of the first die are connected to adjacent input/output pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out package or a chip on wafer on substrate package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

10. 发明公开

EP2863424A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：EP2863424A1
公开(公告)日：2015-04-22
申请号：EP14192248.4
申请日：2004-12-16
申请人： Seiko Epson Corporation
发明人： Ito, Haruki
IPC分类号： H01L23/31
CPC分类号： H01L23/5226 , H01L23/293 , H01L23/3114 , H01L23/3192 , H01L23/49816 , H01L23/5329 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/17 , H01L2224/02125 , H01L2224/02126 , H01L2224/02331 , H01L2224/0236 , H01L2224/02373 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/02381 , H01L2224/024 , H01L2224/11334 , H01L2224/1146 , H01L2224/13014 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/14131 , H01L2224/16225 , H01L2224/16227 , H01L2224/94 , H01L2924/0002 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/013 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/186 , H01L2924/3512 , H01L2924/00 , H01L2224/11
摘要： There is provided a semiconductor device, comprising a substrate (2), a first electrode (9) disposed on a circumferential region of a surface of the substrate (2), a first wiring (4a) disposed on the substrate (2) and connected to the first electrode (9), a first resin layer (3) disposed on the first wiring (4a) and including a via hole (11), a second wiring (4b) disposed on the first insulating layer (3) and connected to the first wiring (4a) through the via hole (11) and a first terminal (7) disposed on the second wiring (4b), wherein the via hole (11) is disposed towards the centre (10) of the surface of the substrate (2) relative to the first electrode (9) and the first terminal (7).
摘要翻译：提供了一种半导体器件，包括衬底（2），设置在衬底（2）的表面的圆周区域上的第一电极（9），设置在衬底（2）上并连接到第一布线所述第一电极（9）包括：第一树脂层（3），其设置在所述第一布线（4a）上并且包括通孔（11）;第二布线（4b），其设置在所述第一绝缘层（3）上并且连接到通过通孔（11）的第一布线（4a）和布置在第二布线（4b）上的第一端子（7），其中通孔（11）朝向衬底表面的中心（10）（2）相对于第一电极（9）和第一端子（7）。

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