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1. 发明公开

EP4364146A1 MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTIPLEXING 审中-公开
公开(公告)号：EP4364146A1
公开(公告)日：2024-05-08
申请号：EP22743979.1
申请日：2022-06-16
申请人： QUALCOMM INCORPORATED
发明人： SAHU, Rahul , GUPTA, Sharad Kumar , KIM, Jung Pill , JUNG, Chulmin , ABRAHAM, Jais
IPC分类号： G11C29/02 , G11C29/00 , G11C29/24 , G11C29/32 , G11C29/12 , G11C29/46
CPC分类号： G11C29/32 , G11C29/24 , G11C29/024 , G11C29/848 , G11C2029/320220130101 , G11C29/46 , G11C29/781 , G11C2029/120420130101

2. 发明授权

EP1376610B1 Block redundancy implementation in hierarchical RAMs 有权
标题翻译：在分层RAM存储器实现块冗余
公开(公告)号：EP1376610B1
公开(公告)日：2011-09-14
申请号：EP03014062.8
申请日：2003-06-23
申请人： Broadcom Corporation
发明人： Terzioglu, Esin , Winograd, Gil I. , Afghahi, Morteza Cyrus
IPC分类号： G11C29/00 , G11C11/417
CPC分类号： G11C29/81 , G06F13/4086 , G11C7/06 , G11C7/18 , G11C11/41 , G11C11/419 , G11C29/808 , G11C29/848 , Y02D10/14 , Y02D10/151
摘要： The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines (3202) or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder (3200A-3200D) adapted to be shifted out of use; and at least one redundant predecoder (3200E) adapted to be shifted in to use.

3. 发明授权

EP1262996B1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译： INTEGRIERTES HALBLEITERSCHALTUNGSBAUELEMENT
公开(公告)号：EP1262996B1
公开(公告)日：2010-12-15
申请号：EP01904349.6
申请日：2001-02-08
申请人： Hitachi, Ltd.
发明人： ISHIBASHI, Koichiro c/o Hitachi, Ltd. , SYUKURI, Shoji c/o Hitachi, Ltd. , YANAGISAWA, Kazumasa c/o Hitachi, Ltd. , NISHIMOTO, Junichi c/o Hitachi, Ltd. , YAMAOKA, Masanao c/o Hitachi, Ltd. , AOKI, Masakazu c/o Hitachi, Ltd.
IPC分类号： G11C29/00 , H01L21/8247
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor integrated circuit having multilevel interconnection and copper interconnection. The cost of defect remedy of the circuit and the cost of trimming are reduced. Addresses for remedying a defect in a memory array in the semiconductor are stored in a nonvolatile memory device where the first polysilicon layer is used as a floating electrode. The nonvolatile memory device is programmed during the test of the semiconductor integrated circuit. No special process is needed to fabricate the nonvolatile memory device. That is, the nonvolatile memory device can be fabricated in the process of fabricating a CMOS device. Because the nonvolatile memory device is programmed during the test, no laser for programming is needed and the time required for the programming is shortened, thereby reducing the testing cost.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮置电极的非易失性存储元件通过第一（第一）存储来存储半导体中存储单元阵列的缺陷的地址多晶硅层或非易失性存储元件被编程用于测试半导体集成电路。结果，在形成非易失性存储元件时不需要特殊的处理。换句话说，非易失性存储元件可以在形成CMOS器件的过程中形成，并且不需要用于编程的激光束的装置，因为在测试中执行编程。因此，可以缩短编程所需的时间，因此可以降低测试成本。

4. 发明公开

EP1986233A3 On-chip reconfigurable memory 失效
标题翻译：可重构片上存储器
公开(公告)号：EP1986233A3
公开(公告)日：2010-08-04
申请号：EP08006005.6
申请日：1998-04-03
申请人： Leedy, Glenn, J.
发明人： Leedy, Glenn, J.
IPC分类号： H01L25/065 , H01L21/768 , H01L27/06 , H01L27/108 , H01L21/822 , H01L27/105 , H01L21/603 , G11C29/00 , G11C29/44
CPC分类号： H01L27/10897 , G11C5/02 , G11C5/025 , G11C5/04 , G11C29/44 , G11C29/81 , G11C29/846 , G11C29/848 , H01L23/481 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29116 , H01L2224/29118 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/8083 , H01L2225/06541 , H01L2924/01079 , Y10S438/977 , H01L2924/00014
摘要： An on-chip reconfigurable memory is disclosed, comprising: a plurality of data lines, a plurality of gate lines, an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines, a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment and a controller for determining that at least one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

5. 发明公开

EP2006859A9 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：EP2006859A9
公开(公告)日：2009-05-20
申请号：EP06730215.8
申请日：2006-03-28
申请人： Fujitsu Microelectronics Limited
发明人： KOBAYASHI, Hiroyuki
IPC分类号： G11C29/04
CPC分类号： G11C29/848 , G11C7/24
摘要： Regular redundancy lines are provided dedicatedly and respectively corresponding to redundancy fuse circuits in which defect addresses are programmed. A reservation redundancy line is provided in common to the redundancy fuse circuits. Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect.
摘要翻译：常规冗余线专门提供并分别对应于其中编程了缺陷地址的冗余熔丝电路。冗余熔丝电路共同提供预留冗余线。地址比较电路各自将冗余熔丝电路中编程的缺陷地址与访问地址进行比较，并且当比较结果匹配时输出冗余信号。控制开关电路根据从选择熔丝电路输出的冗余选择信号进行切换，并响应于冗余信号使对应的正常冗余线或预留冗余线有效。通过将冗余线划分为正常冗余线和预留冗余线，每个冗余熔丝电路可以通过简单的开关电路而与多条冗余线中的一条相对应。因此，可以减小信号的传播延迟时间的差异，并且可以在减轻缺陷和没有缺陷时减小访问时间的差异。

6. 发明公开

EP2006859A2 SEMICONDUCTOR MEMORY 有权
标题翻译： HALBLEITERSPEICHER
公开(公告)号：EP2006859A2
公开(公告)日：2008-12-24
申请号：EP06730215.8
申请日：2006-03-28
申请人： Fujitsu Ltd.
发明人： KOBAYASHI, Hiroyuki
IPC分类号： G11C29/04
CPC分类号： G11C29/848 , G11C7/24
摘要： Regular redundancy lines are provided dedicatedly and respectively corresponding to redundancy fuse circuits in which defect addresses are programmed. A reservation redundancy line is provided in common to the redundancy fuse circuits. Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect.
摘要翻译：专门提供常规冗余线，分别对应于冗余熔丝电路，其中对缺陷地址进行编程。为冗余保险丝电路提供预留冗余线路。每个地址比较电路将冗余保险丝电路中编程的缺陷地址与访问地址进行比较，并在比较结果匹配时输出冗余信号。控制开关电路根据从选择熔丝电路输出的冗余选择信号进行切换，并根据冗余信号进行相应的规则冗余线路或预留冗余线路的验证。通过将冗余线划分为常规冗余线和预留冗余线，可以利用简单的开关电路使冗余熔丝电路中的每一个对应于多条冗余线之一。因此，可以使信号的传播延迟时间的差异小，并且当不存在缺陷时和不存在缺陷时可以使访问时间的差异较小。

7. 发明授权

EP1315174B1 Semiconductor memory 有权
标题翻译：半导体内存
公开(公告)号：EP1315174B1
公开(公告)日：2008-11-05
申请号：EP02253701.3
申请日：2002-05-27
申请人： FUJITSU LIMITED
发明人： Okuyama, Yoshiaki, c/o Fujitsu Limited , Fujioka, Shinya, c/o Fujitsu Limited , Hara, Kota, c/o Fujitsu Limited , Mori, Katsuhiro, c/o Fujitsu Limited
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/812 , G11C29/848

8. 发明公开

EP1262996A4 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：集成半导体电路元件
公开(公告)号：EP1262996A4
公开(公告)日：2007-06-27
申请号：EP01904349
申请日：2001-02-08
申请人： HITACHI LTD
发明人： ISHIBASHI KOICHIRO , SYUKURI SHOJI , YANAGISAWA KAZUMASA , NISHIMOTO JUNICHI , YAMAOKA MASANAO , AOKI MASAKAZU
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor integrated circuit having multilevel interconnection and copper interconnection. The cost of defect remedy of the circuit and the cost of trimming are reduced. Addresses for remedying a defect in a memory array in the semiconductor are stored in a nonvolatile memory device where the first polysilicon layer is used as a floating electrode. The nonvolatile memory device is programmed during the test of the semiconductor integrated circuit. No special process is needed to fabricate the nonvolatile memory device. That is, the nonvolatile memory device can be fabricated in the process of fabricating a CMOS device. Because the nonvolatile memory device is programmed during the test, no laser for programming is needed and the time required for the programming is shortened, thereby reducing the testing cost.

9. 发明公开

EP1585137A1 Synchronous global controller for enhanced pipelining 有权
标题翻译：一种改进的管线全球同步控制器
公开(公告)号：EP1585137A1
公开(公告)日：2005-10-12
申请号：EP05007574.6
申请日：2003-06-23
申请人： Broadcom Corporation
发明人： Anvar, Ali , Winograd, Gil I. , Terzioglu, Esin
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C11/419 , G06F13/4086 , G11C5/025 , G11C5/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/41 , G11C11/412 , G11C11/413 , G11C29/808 , G11C29/848 , Y02D10/14 , Y02D10/151
摘要： The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

10. 发明公开

EP1408515A1 Sub-column-repair-circuit 有权
标题翻译： Schaltkreis zur Reparatur von Subspalten
公开(公告)号：EP1408515A1
公开(公告)日：2004-04-14
申请号：EP03291292.5
申请日：2003-05-28
申请人： Infineon Technologies AG
发明人： Tellier, Yann
IPC分类号： G11C29/00
CPC分类号： G11C29/848 , G11C29/846
摘要： Memory having pre- and post-column decoders (4) and a sub-column-repair-circuit (1) for replacing a faulty subcolumn having plural bitlines by adjacent regular or redundant subcolumns. To reduce the number of subcolumns that need to be replaced in case of a single bit line failure, the multiplexers (9) controlled by the fusebox (20) of the redundancy circuitry are arranged between the multiplexers (2,13) respectively driven by the pre- and post-column decoders (4).
摘要翻译：可以响应于熔丝数据信号来切换连接到前多路复用器单元（2）的多路复用器（2a-2d）的输出端的中间多路复用器单元（9），用于替换具有相邻的故障存储器子列的故障存储器子列内存子列。可以响应于后解码信号来切换连接到中间多路复用器单元的输出端的多路复用器单元（13）。存储芯片还包括独立的权利要求。

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