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1. 发明授权

EP0411491B1 Method and apparatus for performing division using a rectangular aspect ratio multiplier 失效
标题翻译：一种用于使用乘法器矩形长宽比执行除法的方法和装置
公开(公告)号：EP0411491B1
公开(公告)日：1999-03-03
申请号：EP90114441.0
申请日：1990-07-27
申请人： CYRIX CORPORATION
发明人： Briggs, Willard Stuart , Matula, David William
IPC分类号： G06F7/52 , G06F7/49
CPC分类号： G06F7/535 , G06F7/4917 , G06F7/5375 , G06F2207/5351 , G06F2207/5355

2. 发明授权

EP0450751B1 High speed digital divider 失效
标题翻译：快速数字分频器
公开(公告)号：EP0450751B1
公开(公告)日：1998-12-16
申请号：EP91301347.0
申请日：1991-02-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Shah, Salim A. , Lynch, Thomas W.
IPC分类号： G06F7/50 , G06F7/52
CPC分类号： G06F7/509 , G06F7/535 , G06F7/5375

3. 发明授权

EP0356153B1 Radix-2**n divider method and apparatus using overlapped quotient bit selection and concurrent quotient rounding and correction 失效
标题翻译：为基2 ** N-司与重叠Quotientenbitauswahl和同时校正和舍入的商的方法和装置。
公开(公告)号：EP0356153B1
公开(公告)日：1995-09-27
申请号：EP89308375.8
申请日：1989-08-17
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kehl, Theodore H. , Cutler, David N.
IPC分类号： G06F7/52 , H03M7/12
CPC分类号： G06F7/535 , G06F7/49963 , G06F7/5375 , G06F2207/3844 , H03M7/12

4. 发明公开

EP0658256A1 HIGH PERFORMANCE MANTISSA DIVIDER 失效
标题翻译：高性能的MANTISSA DIVIDER
公开(公告)号：EP0658256A1
公开(公告)日：1995-06-21
申请号：EP93919859.0
申请日：1993-07-26
申请人： CRAY RESEARCH, INC.
发明人： SMITH, James, E.
IPC分类号： G06F7
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49947 , G06F7/5375
摘要： A high performance floating point mantissa divider employs SRT division, a Radix-4 redundant digit set and the principles of carry-save addition. At each step in the division, the upper few most significant bits of the partial remainder and the divisor are inspected via a look-up table to select the appropriate quotient digits. The quotient digits are represented in a Radix-4 redundant digit set, and the look-up table is generated using SRT division principles. The selected quotient digit is used to control a multiplexor which selects the selected multiple of the divisor. This value is substracted from the partial remainder via a carry-save adder to form the new partial remainder. As the quotient digits are generated, they are placed in two shift registers, one for the sum digits and one for carry digits. When the division is complete, the shift registers are added to give the final quotient mantissa. A combination of a carry save adder and carry lookahead adder reduce the practical implementation to only 8 logic levels.
摘要翻译：高性能浮点尾数分频器采用SRT分频，基数-4冗余数字集和进位保存加法原理。在除法中的每一步中，部分余数和除数的高几位最重要的位通过查找表进行检查，以选择适当的商数字。商数字用基数-4冗余数字集表示，并且使用SRT分割原理生成查找表。所选商数字用于控制选择所选倍数除数的多路复用器。该值通过进位保存加法器从部分余数中减去以形成新的部分余数。随着商数字的产生，它们被放置在两个移位寄存器中，一个用于总数字，另一个用于进位数字。分区完成后，移位寄存器被添加到最后的商尾数。进位保存加法器和进位先行加法器的组合将实际实现减少到只有8个逻辑电平。

5. 发明公开

EP0464493A3 High-radix divider 失效
标题翻译：高分辨率分辨率
公开(公告)号：EP0464493A3
公开(公告)日：1993-08-18
申请号：EP91110168.1
申请日：1991-06-20
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mori, Junji, c/o Intellectual Property Div.
IPC分类号： G06F7/52 , G06F7/49
CPC分类号： G06F7/535 , G06F7/49 , G06F7/5375
摘要： A dividend or partial remainder (R (j) ) is stored in a partial remainder register (1). An output of the partial remainder register (1) is shifted to the left by a radix which uses the power of 2 and is larger than 2. A divisor (D) is stored in a divisor register (2). Comparison constants obtained by subjecting an output of the divisor register (2) to predetermined operations are stored in comparison constant registers (3-1, 3-2). Subtracters (5-1, 5-2) respectively receive outputs of the comparison constant registers as one input, receive upper bits of a bit number representing a precision required for conversion and included in the output of the partial remainder shifter (4) as another input, and compare the magnitudes of the two inputs with each other to derive partial quotients. A selector (6) shifts and selects an output of the divisor register (2) according to the signs of the remainder quotients output from the subtracters (5-1, 5-2) to create a factor having a value equal to the integer multiple of the divisor. An adder/subtracter (7) receives an output of the selector (6) and an output of the partial remainder shifter (4) and the addition or subtraction of the adder/subtracter is selectively specified by the sign bit of an output of the partial remainder shifter (4) to derive a partial remainder (R (j+1) ).

6. 发明公开

EP0460353A3 Symmetrical ratio decoders for binary division 失效
标题翻译：二分法的对称比例解码器
公开(公告)号：EP0460353A3
公开(公告)日：1993-05-26
申请号：EP91101664.0
申请日：1991-02-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Maass, Klaus Karl , Shen, David Tjeng-Ming
IPC分类号： G06F7/52 , G06F7/48 , H03M7/12
CPC分类号： G06F7/535 , F02B2075/027 , G06F7/491 , G06F7/5375 , H03M7/12
摘要： An essentially symmetrical ratio decoder which covers all areas in both the positive and negative regions with only a small number of noted exceptions. Multiple boundaries were selected such that the positive and negative regions were symmetrical with only a small number of exceptions. Using these boundaries, an essentially symmetrical, unified ratio decoder was constructed using only about one-half of the integrated circuit real estate of conventional ratio decoder pairs. By decoding the sign bit from the ratio decoder adder, the ratio decoder recognizes the exceptional areas and handles them accordingly.

7. 发明授权

EP0192420B1 Method and apparatus for numerical division 失效
标题翻译：数值分析方法与装置
公开(公告)号：EP0192420B1
公开(公告)日：1991-05-15
申请号：EP86300988.2
申请日：1986-02-13
申请人： PRIME COMPUTER, INC.
发明人： Irukulla, Suren , Patel, Bimal V
IPC分类号： G06F7/52 , G06F7/49
CPC分类号： G06F7/535 , G06F7/49 , G06F7/4917 , G06F7/5375

8. 发明公开

EP3286635A1 HIGH PERFORMANCE DIVISION AND ROOT COMPUTATION UNIT 无效
公开(公告)号：EP3286635A1
公开(公告)日：2018-02-28
申请号：EP16714722
申请日：2016-03-28
申请人： QUALCOMM INC
发明人： DIBRINO MICHAEL THOMAS , DOCKSER KENNETH ALAN , LALL PATHIK SUNIL
IPC分类号： G06F7/537 , G06F7/552
CPC分类号： G06F7/52 , G06F7/537 , G06F7/5375 , G06F7/5525 , G06F2207/5528
摘要： Systems and methods relate to a division/root computation unit. A lookup table according to a Sweeney, Robertson, and Tocher (SRT) algorithm for a division/root computation is stored in a memory. Information related to a selected column corresponding to a divisor/root estimate is stored in a high-speed memory. Division/root computation is performed iteratively using the cached information to improve access times and reduce latency of accessing the entire lookup table on each iteration. In each iteration, a quotient/root is determined from the cached information based on a current partial remainder, and a next partial remainder is generated based on the quotient/root, the divisor/root estimate, and the current partial remainder.

9. 发明授权

EP0529101B1 FLOATING-POINT DIVIDING CIRCUIT 失效
标题翻译：对于浮点除法器
公开(公告)号：EP0529101B1
公开(公告)日：1998-10-21
申请号：EP92906716.3
申请日：1992-03-12
申请人： FUJITSU LIMITED
发明人： KUROIWA, Koichi, Fujitsu Limited
IPC分类号： G06F7/52 , G06F1/32
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/5375

10. 发明授权

EP0658256B1 HIGH PERFORMANCE MANTISSA DIVIDER 失效
标题翻译：高性能的MANTISSA DIVIDER
公开(公告)号：EP0658256B1
公开(公告)日：1998-09-23
申请号：EP93919859.4
申请日：1993-07-26
申请人： CRAY RESEARCH, INC.
发明人： SMITH, James, E.
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49947 , G06F7/5375

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