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    • 2. 发明公开
    • ARRAY SUBSTRATE AND DISPLAY DEVICE
    • 阵列基板和显示装置
    • EP3196692A1
    • 2017-07-26
    • EP15842343.4
    • 2015-01-05
    • BOE Technology Group Co., Ltd.
    • NING, CeWU, ChunweiZHANG, Yuting
    • G02F1/1343
    • H01L27/124G02F1/133345G02F1/134309G02F1/134363G02F1/136G02F2001/134318G02F2001/134372G02F2001/134381G02F2001/13606G02F2201/121H01L27/1248
    • The present invention relates to the field of display technology, particularly to an array substrate and a display device, for solving the problem that the capacitance values of C gc and/or C dc are relatively large in the prior art. One embodiment of the present invention provides an array substrate, comprising: a gate line, a data line, and a common electrode layer electrically insulated from the gate line and the data line, wherein there is at least one overlapping area between the common electrode layer and the gate line, and/or, there is at least one overlapping area between the common electrode layer and the data line; moreover, the common electrode layer comprises a hollow structure part located in the at least one overlapping area, and the hollow structure part located in the overlapping area comprises at least one hollow area. The embodiment of the present invention can reduce the capacitance values of C gc and/or C dc .
    • 本发明涉及显示技术领域,具体涉及一种阵列基板和显示装置,用于解决现有技术中Cgc和/或Cdc的电容值相对较大的问题。 本发明的一个实施例提供了一种阵列基板,包括:栅极线,数据线以及与栅极线和数据线电绝缘的公共电极层,其中公共电极层 所述公共电极层与所述数据线之间至少存在一个重叠区域, 此外,所述公共电极层包括位于所述至少一个重叠区域的中空结构部分,位于所述重叠区域的中空结构部分包括至少一个中空区域。 本发明的实施例可以降低Cgc和/或Cdc的电容值。
    • 8. 发明公开
    • VLSI VISUAL DISPLAY
    • VLSI SICHTANZEIGE
    • EP0846282A1
    • 1998-06-10
    • EP96932162.0
    • 1996-08-26
    • MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    • ALVELDA, PhillipKNIGHT, Thomas, F., Jr.
    • G02B27G02F1
    • G02F1/133621G02B27/017G02B27/0172G02B2027/0132G02B2027/0154G02B2027/0178G02F1/136G02F1/136277G02F2201/305G02F2203/34
    • The present invention provides a visual display including a high resolution miniature display compatible with VLSI technology and an optical system such as an optical magnifier used to enlarge the images display on the miniature display to be visible to the naked eye. The miniature display includes a VLSI backplane having an array of display elements monolithically formed with its driving circuit on a single crystalline semiconductor. Signal processing circuit or a microprocessor used to process image signals for the display may also be formed monolithically with the array and its driving circuit. The array may be designed using a software silicon compiler program to have randomly displaced elements or superpixels for reducing image aliasing. The array may also be designed to have display elements positioned and scaled to compensate for the optical distortion introduced by the magnifier. A color microdisplay utilizes diffraction gratings to provide an array of high efficiency color pixels. The microdisplay includes a semiconductor substrate and source of light disposed adjacent thereto. A cover plate may be disposed above the substrate and has a layer of conductive material on a surface of the cover plate opposite the substrate. An optically active material, such as liquid crystal material, may be disposed between the substrate and the cover plate. An array of pixels are formed on the substrate. The pixel array includes an array of diffraction grating elements. Each element includes one or more diffraction gratings. The pitch of each diffraction grating can be a function of the angle of the incident light and the desired diffraction output spectrum. An optical system directs the diffracted light from each grating through the optically active material into viewing optics.