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1. 发明授权

EP2128763B1 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：待测试集成电路恒定的施加和测试图案减压到设备
公开(公告)号：EP2128763B1
公开(公告)日：2014-01-08
申请号：EP09170518.6
申请日：2000-11-15
申请人： Mentor Graphics Corporation
发明人： Rajski, Janusz , Tyszer, Jerzy , Kassab, Mark , Mukherjee, Nilanjan
IPC分类号： G06F11/00 , G01R31/3181 , G01R31/3183 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/31813 , G01R31/318335

2. 发明公开

EP1975634A3 Decompressor/PRPG for Applying Pseudo-Random and Deterministic Test Patterns 有权
标题翻译：用于产生Dekrompressionsgerat / PRPG伪偶然和确定性Prufmustern
公开(公告)号：EP1975634A3
公开(公告)日：2008-10-15
申请号：EP08104507.2
申请日：2000-11-16
申请人： Mentor Graphics Corporation
发明人： RAJSKI, Janusz , TYSZER, Jerzy , KASSAB, Mark , MUKHERJEE, Nilanjan
IPC分类号： G01R31/3183 , G01R31/3181
CPC分类号： G01R31/31813 , G01R31/318335 , G01R31/318385
摘要： A system for applying test patterns to scan chains (26) in a circuit-under-test (34) comprising:
means (36) for applying test patterns to the scan chains;
means (21) for providing a set of compressed deterministic test patterns to the test pattern applying means;
means (21,25) for providing an initial value to the test pattern applying means; and
means (25) for configuring the test pattern applying means to generate, in a pseudorandom phase of operation, a set of pseudo-random patterns from to the initial value and to generate, in a deterministic phase of operation, a set of decompressed deterministic test patterns from the set of compressed deterministic test patterns.

3. 发明公开

EP1942349A1 Schaltung zur Komprimierung und Speicherung von Schaltungsdiagnosedaten 有权
公开(公告)号：EP1942349A1
公开(公告)日：2008-07-09
申请号：EP08103659.2
申请日：2005-06-17
申请人： Infineon Technologies AG
发明人： Pöhl, Frank Dr. , Beck, Matthias , Muhmenthaler, Peter , Rzeha, Jan , Gössel, Michael Prof. Dr.
IPC分类号： G01R31/3185 , G01R31/319
CPC分类号： G01R31/318335 , G01R31/3185 , G01R31/318566 , G01R31/31921
摘要： Ein Kompakter K hat eine Anzahl M von Testdateneingängen (E 1 , ... ,E M ), die mit Schaltungsausgängen A einer elektrischen Schaltung S verbunden sind. , sowie mit einer Anzahl k von Testvergleichseingängen v 1 i ⋯ v k i und mit einer Anzahl m von Testdatenausgängen (S 1 , ··· , S m ). Der Kompaktor K weist eine Anzahl von H-Matrix-XOR-Gattern (1, 2, 3, 4, 5, 6, 7) aufweist, die als Schaltwerk so zwischen den Testdateneingängen (E 1 , ... , E M ) und den Testdatenausgängen (S 1 , ... , S m ) angeordnet sind, dass die an seinen Testdateneingängen (E 1 , ... ,E M ) anliegenden Daten entsprechend den Koeffizienten einer H-Matrix eines fehlerkorrigierenden Kodes komprimiert an den Testdatenausgängen (S 1 , ... , S m ) anliegen. Der Kompaktor K hat weiterhin Kompensations-XOR-Gatter (11, 12, 13, 14, 15, 16) aufweist, die im Bereich zwischen den Testdateneingängen (E 1 , ... ,E M ) und den Testdatenausgängen (S 1 , ... , S m ) angeordnet sind, wobei jeweils ein Eingang eines Kompensations-XOR-Gatter (11, 12, 13, 14, 15, 16) zur Eingabe eines Kompensationswerts vorgesehen ist.
摘要翻译：该装置具有要被测试或诊断的电子开关，包括用于输入输入数据的一组开关输入和用于输出输出数据的一组开关输出（A1-A8）。压实机（K1）具有与开关输出连接的一组测试数据输入（E1-E8）。压实机具有一组测试比较输入和一组测试数据输出（S1-S4）。为测试数据输出的数据提供了一个存储器件。存储器件在实现开关和比较器的半导体芯片上实现。还包括用于操作电路装置的方法的独立权利要求。

4. 发明授权

EP1734375B1 Schaltung zur Komprimierung und Speicherung von Schaltungsdiagnosedaten 有权
标题翻译：电路，用于压缩和存储诊断数据电路
公开(公告)号：EP1734375B1
公开(公告)日：2008-05-21
申请号：EP05013130.9
申请日：2005-06-17
申请人： Infineon Technologies AG
发明人： Pöhl, Frank Dr. , Beck, Matthias , Muhmenthaler, Peter , Rzeha, Jan , Gössel Michael Prof. Dr.
IPC分类号： G01R31/3185
CPC分类号： G01R31/318335 , G01R31/3185 , G01R31/318566 , G01R31/31921

5. 发明公开

EP1475643A1 Test pattern compression for an integrated circuit test environment 有权
标题翻译： Testmuster-Kompressionfüreine Testumgebung von integrierten Schaltungen
公开(公告)号：EP1475643A1
公开(公告)日：2004-11-10
申请号：EP04017880.8
申请日：2000-11-15
申请人： Mentor Graphics Corporation
发明人： The designation of the inventor has not yet been filed
IPC分类号： G01R31/3185
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test (60). Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit (60). A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell (64). The equations are solved to obtain the compressed test pattern (66).
摘要翻译：一种用于压缩被测电路中扫描链的测试图案的压缩方法。该方法包括生成与扫描链内的扫描单元相关联的符号表达式。通过将变量分配给提供给被测电路的外部输入通道上的位（60）来创建符号表达式。使用符号仿真，将变量应用于解压缩器以获取符号表达式。使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障（60）。通过将测试立方体中的分配值与与相应的扫描单元格相关联的符号表达式进行等价来表示一组方程式（64）。求解等式以获得压缩测试图案（66）。

6. 发明授权

EP1094471B1 Procédé de test de composants électroniques 有权
标题翻译：一种用于测试电子组件的方法
公开(公告)号：EP1094471B1
公开(公告)日：2003-01-02
申请号：EP00402906.2
申请日：2000-10-19
申请人： Softlink
发明人： Lejeune, Philippe
IPC分类号： G11C29/00
CPC分类号： G01R31/318335 , G01R31/318328 , G11C16/04 , G11C29/50

7. 发明公开

EP1242885A2 CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS TO A CIRCUIT-UNDER-TEST 有权
标题翻译：持久应用程序和试件解压结束考试综合电路
公开(公告)号：EP1242885A2
公开(公告)日：2002-09-25
申请号：EP00991744.4
申请日：2000-11-15
申请人： Mentor Graphics Corporation
发明人： RAJSKI, Janusz , TYSZER, Jerzy , KASSAB, Mark , MUKHERJEE, Nilanjan
IPC分类号： G06F11/00
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318547
摘要： A method for applying test patterns to scan chains (26) in a circuit-under-test (24). The method includes providing a compressed test pattern (32) of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor (36)such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

8. 发明公开

EP1074915A1 One-chip microcomputer and control method thereof as well as an ic card having sucha one-chip microcomputer 有权
标题翻译： Ein-Chip-Mikrorechner和dessen Steuerungsverfahren
公开(公告)号：EP1074915A1
公开(公告)日：2001-02-07
申请号：EP00303796.7
申请日：2000-05-05
申请人： SHARP KABUSHIKI KAISHA , Nippon Telegraph and Telephone Corporation
发明人： Wakabayashi, Masaki , Tanno, Masaaki , Suto, Hiroki , Takeda, Tadao
IPC分类号： G06F11/267 , G01R31/3183 , G06F11/22
CPC分类号： G01R31/318335 , G01R31/318385 , G01R31/318392 , G06F11/2236 , G06F11/2273
摘要： In order to provide a built-in self testing function, a one-chip microcomputer is equipped with an activation register for activating the test operation and a built-in self test activation pattern generator for setting initial values at test control circuits (pseudo random number generator, logical circuit testing compressor, pattern generator, and memory testing compressor). In accordance with an instruction from the CPU, a built-in self test is activated so that the results of tests of the memory and the group of logical circuits are read from the memory testing compressor and the logical circuit testing compressor, and respectively compared with expected values preliminarily stored in the memory in the one-chip microcomputer; thus, the results are diagnosed. Thus, it is possible to carry out a built-in self test without using a plurality of exclusively-used test terminals.
摘要翻译：为了提供内置的自检功能，单片机配备有用于激活测试操作的激活寄存器和内置的自检激活模式发生器，用于设置测试控制电路的初始值（伪随机数发电机，逻辑电路测试压缩机，模式发生器和内存测试压缩机）。根据CPU的指令，激活内置自检，从存储器测试压缩器和逻辑电路测试压缩器读取存储器和逻辑电路组的测试结果，并分别与初步存储在单片机中的存储器中的预期值; 因此，诊断结果。因此，可以在不使用多个专用测试端子的情况下进行内置自检。

9. 发明公开

EP0758771A1 An electronic circuit or board tester and a method of testing an electronic device 失效
标题翻译：电子电路或板测试仪和方法，用于测试一电子装置
公开(公告)号：EP0758771A1
公开(公告)日：1997-02-19
申请号：EP95112576.4
申请日：1995-08-10
申请人： Hewlett-Packard GmbH
发明人： Heitele, Winfried , Zschiegner, Stefan
IPC分类号： G06F11/273 , G06F11/263 , G01R31/28
CPC分类号： G01R31/318335 , G01R31/318307 , G01R31/31921
摘要： This invention relates to electronic circuit testing and more particularly to an apparatus and a method utilizing enhanced test data compression techniques. An electronic circuit or board tester according to the invention comprises one tester circuit with a combination of a sequencer and a vector-sequencer-memory per pin. The test-data-sequence to be applied to a pin of a device under test is compressed in order to save memory space.
摘要翻译：本发明涉及电子电路的测试，更具体地装置和利用增强的测试数据压缩技术的方法。一种电子电路或板测试仪gemäß到本发明包括与定序器和每个销的载体序存储器的组合的一个测试器电路。测试数据序列被应用到的装置的测试中的销，以节省存储空间被压缩。

10. 发明公开

EP3090268A1 HANDLING SLOWER SCAN OUTPUTS AT OPTIMAL FREQUENCY 有权
标题翻译：硫磷慢扫描问题进行获取频率
公开(公告)号：EP3090268A1
公开(公告)日：2016-11-09
申请号：EP14875966.5
申请日：2014-12-31
申请人： Texas Instruments Incorporated
发明人： MITTAL, Rajesh, Kumar , KAWOOSA, Mudasir, Shafat , POTTY, Sreenath, Narayanan
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318547 , G01R31/318552
摘要： In described examples of a circuit (200) for testing an integrated circuit, the circuit (200) includes a scan compression architecture (205) driven by a scan clock (230) and generates M scan outputs (220), where M is an integer. A clock divider (232) is configured to divide the scan clock (230) by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic (222) is coupled to the scan compression architecture (205) and generates kM slow scan outputs (224) in response to the M scan outputs (220) and the k phase shifted scan clocks. The packing logic (222) further includes M number of packing elements, and each of the M packing elements receives a respective one of the M scan outputs (220). Each packing element includes k number of flip-flops, and each of the k flip-flops in a packing element receives a respective one of the M scan outputs (220). Each flip-flop receives a respective one of the k phase-shifted scan clocks, such that each flip-flop generates a respective one of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.

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