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1. 发明公开

EP0847038A3 Rendering an audio-visual stream synchronized by a software clock in a personal computer 失效
标题翻译：打一个由软件时钟视听数据流的方式在个人计算机同步
公开(公告)号：EP0847038A3
公开(公告)日：1999-11-03
申请号：EP97309609.2
申请日：1997-11-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McDade, Darryn D. , Owen, Jefferson E.
IPC分类号： G09G5/00
CPC分类号： G11B20/00007 , G06F1/08 , G11B27/105 , G11B27/3027 , H04N5/765
摘要： A DVD CD-ROM player integrated with a personal computer is provided. When integrating a DVD CD-ROM with a personal computer, there are various problems that must be overcome. For example, the stream from the DVD CD-ROM utilizes a 27 MHz clock. However, a personal computer typically does not have a 27 MHz clock, but instead has a system clock, that runs at the frequency of the processor. Therefore, in order to play a DVD-based audio-visual work in a personal computer, a clock running at 27 MHz is needed. As such, a software clock running at 27 MHz is provided which facilitates the integration of a DVD CD-ROM into a personal computer. By using a software clock, synchronization of the audio-visual stream is facilitated and both cost and development time are reduced.

2. 发明公开

EP0730302A3 Vertical switched-emitter structure with improved lateral isolation 失效
标题翻译：垂直开关Emittor结构具有改进的横向隔离
公开(公告)号：EP0730302A3
公开(公告)日：1999-10-13
申请号：EP96301273.7
申请日：1996-02-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Blanchard, Richard A.
IPC分类号： H01L27/07
CPC分类号： H01L29/7813 , H01L27/0605 , H01L27/0716 , H01L27/088 , H01L29/0878 , H01L29/1054 , H01L29/7302 , H01L29/7395 , H01L29/7397 , H01L29/7803 , Y10S148/126
摘要： A vertical switched-emitter device structure in which the body of a vertical-current-flow MOS device is formed in a P-type surface epi region, and dielectric isolation laterally separates the body from the surface contact to the buried P-type base region.

3. 发明公开

EP0854555A3 Integrated supply protection 失效
标题翻译： Schutz einer integrierten Stromversorgung
公开(公告)号：EP0854555A3
公开(公告)日：1999-09-01
申请号：EP97310049.8
申请日：1997-12-12
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Notaro, Joseph , Swanson, David Frank
IPC分类号： H02H11/00
CPC分类号： H02H11/003 , H02H9/046 , Y10T307/839
摘要： An electrical power protection integrated circuit provides protection against reverse battery and overvoltage conditions that is particularly of value in automotive applications in which reverse battery and overvoltage conditions are commonplace. The electrical power protection integrated circuit device contains a reverse battery condition protection element, supplied either directly or indirectly from a battery power source, that protects against a reverse battery condition of the battery power source and an overvoltage protection element coupled to the reverse battery condition protection device that protects against an overvoltage condition of the battery power source and produces a protected power output that is isolated from both battery overvoltage and reverse battery voltage conditions. Additionally, the integrated circuit device can further produce an auxiliary protected power output that is isolated from reverse battery voltage conditions.
摘要翻译：电力保护集成电路提供防止反向电池和过电压条件的保护，这在特别是在反向电池和过电压条件是常见的汽车应用中是有价值的。电力保护集成电路装置包含反向电池状态保护元件，其直接或间接地从电池电源提供，其防止电池电源的反向电池状态和与反向电池状态保护耦合的过电压保护元件该装置可以防止电池电源的过压状态，并产生与电池过电压和反向电池电压条件隔离的受保护的电源输出。此外，集成电路器件可以进一步产生与反电池电压条件隔离的辅助受保护功率输出。

4. 发明公开

EP0851555A3 Integrated circuit with improved overvoltage protection 失效
标题翻译：具有改进的过电压保护集成电路
公开(公告)号：EP0851555A3
公开(公告)日：1999-08-25
申请号：EP97310081.1
申请日：1997-12-12
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Waggoner, Charles D.
IPC分类号： H02H9/04
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： A special rail is provided along each edge of an integrated circuit chip with bias circuits connected to the ends of each special rail. The bias circuits charge the special rail to the V DD voltage level during normal operation, and clamp the special rail to the V SS rail upon the occurrence of an overvoltage event. Input bonding pads are provided along each edge of the chip and are connected through diodes to the special rail so that 5 volt signals applied to the input bonding pads do not cause damage to the device when operated from a 3.3 volt supply. A signal line of extended length is provided between each input bonding pad and its receiver circuit and includes folded portions for adding to the length of the signal line to form a high frequency inductor to protect the receiver circuit at the onset of an overvoltage event before clamping becomes effective.

5. 发明公开

EP0855797A3 Junction capacitor compensation for wave shaping 失效
标题翻译：半导体结电容与波形整形补偿
公开(公告)号：EP0855797A3
公开(公告)日：1999-07-21
申请号：EP98300289.0
申请日：1998-01-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Edwards, William Ernest , Notaro, Joseph
IPC分类号： H03K5/01
CPC分类号： H03K5/01 , H03K5/06
摘要： A method and structure for wave-shaping of digital waveforms of integrated circuit processes that do not have area efficient dielectric capacitors is disclosed. The dielectric capacitors of the prior art are replaced with a first, linearizing diode and a second diode of a wave-shaping circuit, each diode having a junction capacitance that varies with voltage applied across the diode. The first, linearizing diode is supplied with a constant current from a constant current source. A current inversely proportional to the junction capacitance of the first, linearizing diode is produced at a node defined as the connection between the constant current source and the first linearizing diode. The current at the node is supplied to the second diode to produce an output voltage of the wave-shaping circuit that is linear with respect to time.

6. 发明公开

EP0786865A3 A precision oscillator circuit 失效
标题翻译：精密振荡器电路
公开(公告)号：EP0786865A3
公开(公告)日：1999-05-26
申请号：EP97300509.3
申请日：1997-01-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Danstrom, Eric J.
IPC分类号： H03K3/0231 , G01P1/07
CPC分类号： G01P3/48 , G01P1/07 , H03K3/011 , H03K3/017 , H03K3/0231
摘要： A precision oscillator constructed from a reference current generator, a charge control stage, a capacitor, a comparator, and a voltage threshold generator is disclosed. The reference current generator generates a reference current which is used by the charge control stage to either charge or discharge the capacitor. The comparator compares the voltage on the capacitor to one of two voltages from the voltage threshold generator. The frequency of oscillation is controlled by an external resistor and an external capacitor. Alternatively, the frequency of oscillation can be controlled by adding or subtracting parallel transistors in a current mirror in the reference current generator.

7. 发明公开

EP0730307A3 FET technology with dielectrically isolated sources and drains 失效
标题翻译： FET技术与介电隔离的源和汇
公开(公告)号：EP0730307A3
公开(公告)日：1999-05-06
申请号：EP96301271.1
申请日：1996-02-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Blanchard, Richard A.
IPC分类号： H01L29/08 , H01L21/336
CPC分类号： H01L29/66651 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/0921 , H01L29/0653 , H01L29/1033 , H01L29/1037 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.

8. 发明公开

EP0877425A3 Field effect device with polycrystalline silicon channel 失效
标题翻译： Feldeffektanordnung mit einem Kanal aus polykristallinem Silizium
公开(公告)号：EP0877425A3
公开(公告)日：1999-04-21
申请号：EP98201854.1
申请日：1991-05-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Chan, Tsiu C. , Guritz, Elmer H. , Han, Yu-Pin
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/0605 , H01L27/1104 , H01L27/1108 , H01L27/1112 , H01L28/20
摘要： A CMOS SRAM cell having first and second field effect devices connected as an inverter. The first field effect device is n-channel and has both its source and drain in a substrate and its gate formed from a first polysilicon layer. The second field effect device has both its source and drain formed in the first polysilicon layer with its gate formed from the substrate. An electrical connection is formed between the drain of the first field effect device in the substrate and the drain of the second field effect device in the first polysilicon layer, this connection may be a diode connection. An electrical connection is formed between the gates of the first field effect device in the first polysilicon layer and the gate of the second field effect device in the substrate. The first and second field effect devices are thereby connected as an inverter.
摘要翻译： CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。在该多晶硅信号线内制造场效应器件。场效应器件的沟道通过薄栅介质与衬底中的有源区域分离，衬底内的有源区域用作场效应器件的控制栅极。这种器件可用于提供用于CMOS SRAM单元的多晶硅P沟道晶体管。

9. 发明公开

EP0846997A3 Integrated circuit actively biasing the threshold voltage of transistors and related methods 失效
标题翻译：晶体管主动地偏置半导体集成电路和相关联的方法的阈值电压
公开(公告)号：EP0846997A3
公开(公告)日：1999-02-10
申请号：EP97309488.1
申请日：1997-11-25
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Siucheong So, Jason , Chan, Tsiu Chiu
IPC分类号： G05F3/24
CPC分类号： G05F3/242
摘要： An integrated circuit includes a plurality of MOSFETs having channels of a first conductivity type, and having active control of an effective threshold voltage of the MOSFETs to be less than an absolute value of an initial threshold voltage. In this embodiment, a first MOSFET has a channel of the first conductivity type, and a second MOSFET is connected to the first MOSFET and has a channel of a second conductivity type. The second MOSFET is preferably biased to a pinch-off region and cooperates with the first MOSFET for generating a control signal related to an effective threshold voltage of the first MOSFET. Moreover, the circuit preferably generates a bias voltage to the plurality of MOSFETs and to the first MOSFET based upon the control signal to set an effective threshold voltage of the plurality of MOSFETs to have an absolute value less than an absolute value of the initial threshold voltage and, more preferably, to a reference voltage. Accordingly, lower supply voltages can be readily accommodated. In another embodiment, the biasing is only provided to activated circuit portions. Method aspects of the invention are also disclosed.

10. 发明公开

EP0886280A1 Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof 失效
标题翻译：一种用于压力测试方法与存储器和集成的电路的集成电路与存储器测试器用于应力
公开(公告)号：EP0886280A1
公开(公告)日：1998-12-23
申请号：EP98303802.7
申请日：1998-05-14
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： So, Jason Siucheong
IPC分类号： G11C29/00
CPC分类号： G11C29/28 , G11C11/41 , G11C29/34 , G11C29/50 , G11C29/56
摘要： An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on the substrate, at least one bit line connected to each of the plurality of memory cells and defining a column, at least one word line connected to each of the plurality of memory cells and defining a row, and sense amplifying means connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns. The integrated circuit also includes a selectable stress tester on the substrate and connected to the memory block for selectively stress testing only portions of the memory block and not other portions so as to determine whether to accept or reject a memory block.
摘要翻译：一种集成电路，具有增强的检测能力并且提供集成电路的测试的方法。集成电路优选地包括基板和在基板上的存储块。存储器块优选地具有在基片上的限定区域内的行中的多个和列排列的多个存储单元的复数，连接到每个存储单元的所述多个所述至少一个位线和限定一列中，至少，连接到每个存储单元的多元性和一个限定行的一条字线，并读出放大连接到所述至少一个位线用于在列的多个所述至少一个感测被寻址的存储器单元的状态的装置。因此，该集成电路包括在衬底上的可选择的应力测试器和连接到用于选择性地应力测试存储器块仅部分而不是其他部分，以便确定是否矿接受或拒绝一个存储器块中的存储器块。

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