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1. 发明公开

EP4305866A1 COEXISTENCE BETWEEN COMMUNICATIONS IN A MOBILE COMMUNICATIONS SYSTEM AND A RADAR APPLICATION 审中-实审
公开(公告)号：EP4305866A1
公开(公告)日：2024-01-17
申请号：EP21712451.0
申请日：2021-03-11
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： SANDGREN, Magnus , KALANTARI, Ashkan , REIAL, Andres , ZOU, Gang , SJÖLAND, Henrik
IPC分类号： H04W16/14 , G01S7/00 , G01S7/02 , G01S13/88 , H04W48/02 , H04W84/04 , H04W88/06

2. 发明公开

EP4121824A1 TIME-TO-DIGITAL CONVERTER CIRCUITRY 审中-实审
公开(公告)号：EP4121824A1
公开(公告)日：2023-01-25
申请号：EP20711928.0
申请日：2020-03-17
申请人： Telefonaktiebolaget LM ERICSSON (PUBL)
发明人： ABDULAZIZ, Mohammed , SJÖLAND, Henrik , PÅHLSSON, Tony
IPC分类号： G04F10/00

3. 发明公开

EP3997917A1 WAKE-UP PACKET BASED COORDINATION OF BROADCASTING DEVICE RESPONSES 审中-实审
公开(公告)号：EP3997917A1
公开(公告)日：2022-05-18
申请号：EP19740540.0
申请日：2019-07-12
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： LOPEZ, Miguel , HIERTZ, Guido, Roland , SJÖLAND, Henrik , WILHELMSSON, Leif
IPC分类号： H04W52/02

4. 发明公开

EP3925078A1 A DIFFERENTIAL COMBINER CIRCUIT 有权
公开(公告)号：EP3925078A1
公开(公告)日：2021-12-22
申请号：EP19705342.4
申请日：2019-02-14
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： SJÖLAND, Henrik
IPC分类号： H04B1/58 , H03H7/46 , H03H9/70 , H04B1/52 , H04B1/56

5. 发明公开

EP3844880A1 CALIBRATION TECHNIQUE FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS 审中-公开
公开(公告)号：EP3844880A1
公开(公告)日：2021-07-07
申请号：EP18765082.5
申请日：2018-08-31
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： SJÖLAND, Henrik , PALM, Mattias
IPC分类号： H03M1/10 , H03M1/12 , H03M1/06

6. 发明公开

EP3826171A1 FINE FREQUENCY DIGITAL OSCILLATOR TUNING 审中-公开
公开(公告)号：EP3826171A1
公开(公告)日：2021-05-26
申请号：EP20198986.0
申请日：2016-10-07
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： SJÖLAND, Henrik , SANDSTRÖM, Torbjörn
IPC分类号： H03B5/12
摘要： A switched capacitor arrangement (200) for tuning a differential circuit is disclosed. The switched capacitor arrangement (200) comprises a first node (211), a second node (212) and a third node (213). The switched capacitor arrangement (200) further comprises a first capacitor (C1) coupled between the first node (211) and the second node (212), a second capacitor (C2) coupled between the second node (212) and the third node (213), and a first switch branch comprising a first switch (S1) coupled between the second node (212) and a signal ground node. The first switch (S1) has an on state and an off state. The first node (211) and third node (213) are configured to be connected to respective differential nodes (Vtank, -Vtank) of the differential circuit. The switched capacitor arrangement (200) is configured to tune the differential circuit by controlling the state of the first switch (S1).

7. 发明公开

EP3616322A1 DIGITAL-TO-ANALOG CONVERSION CIRCUIT 审中-公开
公开(公告)号：EP3616322A1
公开(公告)日：2020-03-04
申请号：EP17720073.0
申请日：2017-04-25
申请人： Telefonaktiebolaget LM Ericsson (PUBL)
发明人： FREDRIKSSON, Henrik , SJÖLAND, Henrik , ANDERSON, Martin
IPC分类号： H03M1/66 , H03M1/80

8. 发明公开

EP3440775A1 PHASE LOCKED LOOP, PHASE LOCKED LOOP ARRANGEMENT, TRANSMITTER AND RECEIVER AND METHOD FOR PROVIDING AN OSCILLATOR SIGNAL 有权
公开(公告)号：EP3440775A1
公开(公告)日：2019-02-13
申请号：EP16714945.9
申请日：2016-04-08
申请人： Telefonaktiebolaget LM Ericsson (PUBL)
发明人： SJÖLAND, Henrik , PÅHLSSON, Tony
IPC分类号： H03L7/087 , H03L7/085
摘要： A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.

9. 发明公开

EP3311492A1 QUADRATURE PHASE DETECTOR CIRCUIT, QUADRATURE PHASE CORRECTOR, MULTI-ANTENNA RADIO CIRCUIT, RADIO STATION AND METHOD 有权
标题翻译：正交相位检测器电路，正交相位校正器，多天线无线电电路，无线电台和方法
公开(公告)号：EP3311492A1
公开(公告)日：2018-04-25
申请号：EP15730128.4
申请日：2015-06-16
申请人： Telefonaktiebolaget LM Ericsson (PUBL)
发明人： EK, Staffan , MATTISSON, Sven , PÅHLSSON, Tony , SJÖLAND, Henrik
IPC分类号： H03L7/085 , H03L7/18 , H03L7/22
CPC分类号： H03L7/085 , H03L7/18 , H03L7/22 , H04B1/04 , H04B7/08 , H04B2001/0491
摘要： A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed. The quadrature phase detector comprises a first circuit arranged to collect a first state value indicating an inner state of a first quadrature signals generating frequency divider circuit of a first frequency synthesizer of the plurality of frequency synthesizers and a second state value indicating an inner state of a second quadrature signals generating frequency divider circuit of a second frequency synthesizer of the plurality of frequency synthesizers, a second circuit arranged to determine from the first state value and the second state value whether quadrature signals of the first frequency synthesizer and quadrature signals of the second frequency synthesizer are in-phase or out-of-phase, and a third circuit arranged to provide an output signal indicating whether the quadrature signals of the first frequency synthesizer and the quadrature signals of the second frequency synthesizer are in-phase or out-of-phase.

10. 发明授权

EP2870699B1 TRANSCEIVER FRONT-END 有权
标题翻译：收发器前端
公开(公告)号：EP2870699B1
公开(公告)日：2017-09-06
申请号：EP12733150.2
申请日：2012-07-09
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ANDERSSON, Stefan , DIN, Imad ud , ECKERBERT, Daniel , SJÖLAND, Henrik , TIRED, Tobias , WERNEHAG, Johan
IPC分类号： H04B1/52
CPC分类号： H04B1/525 , H04B2203/5491 , Y10T29/49117
摘要： A transceiver front-end of a communication device comprises a frequency blocking arrangement, which may be either a transmit frequency blocking arrangement or a receive frequency blocking arrangement. The frequency blocking arrangement has a blocking frequency interval associated with one of a transmit frequency and receive frequency, and a non-blocking frequency interval associated with the other of the transmit frequency and receive frequency. The frequency blocking arrangement is configured to block passage of signals in the blocking frequency interval between said signal transmission and reception node and either said receiver node or said transmitter node. The frequency blocking arrangement comprises a network of passive components comprising at least one transformer and a filter arrangement adapted to have a higher impedance value in the blocking frequency interval than in the non-blocking frequency interval.
摘要翻译：通信设备的收发器前端包括频率阻塞装置，其可以是发射频率阻塞装置或接收频率阻塞装置。频率阻塞装置具有与发射频率和接收频率中的一个相关联的阻塞频率间隔以及与发射频率和接收频率中的另一个相关联的非阻塞频率间隔。频率阻塞装置被配置为阻止信号在所述信号发送和接收节点与所述接收器节点或所述发送器节点之间的阻止频率间隔中的通过。频率阻塞装置包括无源部件的网络，该无源部件包括至少一个变压器和适于在阻塞频率区间中具有比在非阻塞频率区间中更高的阻抗值的滤波器装置。

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