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    • 2. 发明公开
    • Method of increasing the brightness of a display system
    • Verfahren zur Steigerung der Helligkeit eines Anzeigesystems
    • EP0899710A2
    • 1999-03-03
    • EP98202870.6
    • 1998-08-26
    • TEXAS INSTRUMENTS INCORPORATED
    • Pettit, Gregory S.Hewlett, Gregory J.Markandey, Vishal
    • G09G3/34
    • G09G3/2029G09G3/34G09G3/346G09G2310/0235G09G2310/061G09G2320/0626
    • A method of increasing the brightness of a pulse width modulation display system. Image bits are displayed during display periods having a non-binary relationship. The display period of an object bit 902 is set equal to a minimum data load time, and the display periods of all other bits are initially set to have a binary relationship with the object bit. The display periods of at least one non-object bit 904, 906, 908 are then reduced in order to reduce the total frame time to no more than the available useable frame time 910. Preferably, only the display periods of bit of significance greater than the object bit are reduced. The reduction of display periods is guided by Weber's law, in order to prevent the non-binary steps from being noticeable or objectionable to the viewer.
    • 一种增加脉宽调制显示系统的亮度的方法。 在具有非二进制关系的显示周期期间显示图像位。 对象位902的显示周期被设置为等于最小数据加载时间,并且所有其他位的显示周期被初始设置为与对象位具有二进制关系。 然后减少至少一个非对象比特904,906,908的显示周期,以便将总帧时间减少到不超过可用的可用帧时间910.优选地,仅显着大小的显示周期大于 物位减少。 显示周期的减少以韦伯定律为指导,以防止非二进制步骤对观察者显着或令人反感。
    • 3. 发明公开
    • Optical scanning with overlap
    • Überlappendeoptische Abtastung
    • EP0709802A3
    • 1997-12-10
    • EP95117184.2
    • 1995-10-31
    • TEXAS INSTRUMENTS INCORPORATED
    • Florence, James M.Gove, Robert J.Markandey, Vishal
    • G06K15/12
    • H04N1/1903B41J2/45G06K15/1247G06K15/1252G06K2215/111G09G3/002G09G3/20G09G3/2022G09G2340/0407G09G2340/0414G09G2340/0421G09G2340/0442G09G2360/02H04N1/193H04N1/1934H04N1/195H04N1/19584H04N5/7458H04N7/01H04N9/12H04N2005/7466
    • The present invention provides a method of ameliorating the effects of misalignment between modulator arrays, and a system using the same. The ability reduce the effects of misalignment allows multiple, smaller, more cost effective arrays to be used instead of one large array. This can reduce the manufacturing costs of the array, especially arrays that are produced using semiconductor manufacturing processes such as the digital micromirror device. To avoid visual artifacts caused by the misalignment of two or more modulator arrays 1702, 1704, the individual arrays are overlapped and the portion of the image is generated by both arrays. The contribution to the combined output by the overlapping arrays varies, with each array making a small contribution to the overlapped area 1706 at one end and a large contribution at the other end of the overlapped area 1706. Because the overlapping portions of the modulator arrays 1712 collectively form a portion of the image, the alignment error is effectively spread over the entire overlapping portion 1706 and is much less noticeable.
    • 本发明提供了一种改善调制器阵列之间的未对准的效果的方法和使用其的系统。 降低失准影响的能力允许使用多个,更小,更具成本效益的阵列而不是一个大阵列。 这可以降低阵列的制造成本,特别是使用诸如数字微镜器件的半导体制造工艺制造的阵列。 为了避免由两个或更多个调制器阵列1702,1704的未对准引起的视觉伪影,各个阵列重叠,并且图像的部分由两个阵列产生。 由重叠阵列对组合输出的贡献是不同的,每个阵列在一端对重叠区域1706做出小的贡献,并且在重叠区域1706的另一端具有很大的贡献。因为调制器阵列1712的重叠部分 共同形成图像的一部分,对准误差有效地分散在整个重叠部分1706上,并且不太明显。
    • 7. 发明公开
    • Method and apparatus for image processing
    • Verfahren undGerätzur Bildverarbeitung。
    • EP0571121A2
    • 1993-11-24
    • EP93303624.6
    • 1993-05-11
    • TEXAS INSTRUMENTS INCORPORATED
    • Markandey, VishalFlinchbaugh, Bruce E.
    • G06F15/70
    • G06T7/269
    • An image processor (10) is provided in which imaging data obtained by an image sensor (12) is processed for purposes of detecting motion. An optical flow field generator (16) processes the image data to provide condition number-based smoothed optical flow vectors, and stores those smoothed vectors in memory (18). The optical flow field stored in memory (18) is accessed and further processed by analyzer (20) for purposes of providing users with information on the motion of objects in the image plane of image sensor (12). Such user information may be displayed on a monitor (22).
    • 提供了一种图像处理器(10),其中处理由图像传感器(12)获得的成像数据用于检测运动。 光流场发生器(16)处理图像数据以提供基于条件数的平滑光流向量,并将那些平滑矢量存储在存储器(18)中。 存储在存储器(18)中的光流场被分析器(20)进一步处理,以便为用户提供关于图像传感器(12)的图像平面中的物体的运动的信息。 这样的用户信息可以显示在监视器(22)上。
    • 8. 发明公开
    • Microprocessor with improved instruction set architecture
    • 麻省理工学院学士学位论文Befehlsatzarchitektur
    • EP1102163A3
    • 2005-06-29
    • EP00310098.9
    • 2000-11-14
    • Texas Instruments Incorporated
    • Hoyle, DavidGolston, Jeremiah E.Zbiciak, Joseph R.Markandey, VishalSimar, Jr.,Laurence R.Stotzer, Eric J.
    • G06F15/80G06F9/302
    • G06F9/3891G06F9/30014G06F9/30036G06F9/30112G06F9/3012G06F9/3555G06F9/3824G06F9/3828G06F9/3853G06F9/3885
    • A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases that involve fetch/decode units lOa-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Multi-field arithmetic/logic unit (ALU) circuitry (L1, L2, S1, S2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N1 fields, such that the multi-field result includes N1 results corresponding to the set of N1 fields. Multi-field multiplication circuitry (M1, M2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N2 fields, such that the multi-field result includes N2 results corresponding to the set of N2 fields. An instruction set architecture (ISA) is provided that is optimized for intensive numeric algorithm processing and includes a set of single instruction, multiple data (SIMD) instructions to direct the operation of the multi-field ALU circuitry and the multi-field multiplication circuitry. Non-aligned data transfer to data memory (D1, D2, 22) can be performed for byte, half word, word, and double-word data items.
    • 在具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50,其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1在指令执行管线 其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的几个执行阶段。微处理器1的流水线是不受保护的,从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间 存储在指令存储器23中的系统程序代码。提供多场算术/逻辑单元(ALU)电路(L1,L2,S1,S2),用于对一组源操作数进行操作,以形成多场目的地操作数, 将多个源操作数作为一组N1字段进行处理,使得多字段结果包括对应于该组N1字段的N1个结果。 提供多场乘法电路(M1,M2),用于通过将多个源操作数视为一组N2字段来操作一组源操作数以形成多场目的地操作数,使得多场结果包括 N2结果对应于一组N2场。 提供了针对密集数字算法处理进行了优化的指令集架构(ISA),并且包括一组单指令,多数据(SIMD)指令以指导多场ALU电路和多场乘法电路的操作。 可以对字节,半字,字和双字数据项执行非对齐数据传输到数据存储器(D1,D2,22)。