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1. 发明公开

EP0828254A3 Improvements in or relating to semiconductor memory devices 失效
标题翻译：半导体存储器件的改进
公开(公告)号：EP0828254A3
公开(公告)日：1998-12-30
申请号：EP97306887.7
申请日：1997-09-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Masashi
IPC分类号： G11C7/06
CPC分类号： G11C7/06
摘要： A memory unit 30 is provided with a first and second sense amplifier array 32A and 32B. The storage cells 31 of the memory unit are coupled to both sense amplifier arrays. A control unit 34 is provided which controls the operation of the two sense amplifier arrays. The control unit determines through which sense amplifier array data signals are transferred to and from the storage cells. The sense amplifier array not exchanging signals with the I/O terminals can perform the precharge operations and write-back operations. Synchronous operation of the memory unit and a data processing unit can be maintained by alternating the sense amplifier array performing the current memory access operation.
摘要翻译：存储器单元30设置有第一和第二读出放大器阵列32A和32B。存储器单元的存储单元31耦合到两个读出放大器阵列。提供控制单元34，其控制两个读出放大器阵列的操作。控制单元确定通过哪些读出放大器阵列数据信号被传送到存储单元和从存储单元传送。不与I / O端子交换信号的读出放大器阵列可以执行预充电操作和回写操作。存储器单元和数据处理单元的同步操作可以通过交替执行当前存储器存取操作的读出放大器阵列来维持。

2. 发明公开

EP0590591A2 Static random access memory for gate array devices 失效
标题翻译：静态RAM存储器，用于门阵列器件。
公开(公告)号：EP0590591A2
公开(公告)日：1994-04-06
申请号：EP93115622.8
申请日：1993-09-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Masashi
IPC分类号： H03K19/177 , G11C11/412 , H03K3/01 , H01L27/118
CPC分类号： H03K3/012 , G11C11/412
摘要： A gate array device (10) includes a plurality of static random access memory cells (11). Each memory cell (11) comprises n-channel pass gate transistors (12, 14), n-channel drive transistors (16, 18), and p-channel transistors (20, 22). All transistors within the memory cell (11) are approximately of the same size. A resistance element (23) connects to the p-channel transistors (20, 22) in each memory cell (11), generating a new apply voltage ( V ¯ cr ). The resistance element (23) effectively reduces the size of the p-channel transistors (20, 22) to below the size of the drive transistors (16, 18). By effectively reducing the size of the p-channel transistors (20, 22), the speed, accuracy, and stability of the memory cell (11) are enhanced despite the similar sizes of the transistors in the gate array device (10).

3. 发明授权

EP0590591B1 Static random access memory for gate array devices 失效
标题翻译：用于门阵列器件的静态RAM存储器
公开(公告)号：EP0590591B1
公开(公告)日：1998-08-26
申请号：EP93115622.8
申请日：1993-09-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Masashi
IPC分类号： H03K19/177 , G11C11/412 , H03K3/01 , H01L27/118
CPC分类号： H03K3/012 , G11C11/412

4. 发明公开

EP0587443A3 Image processor and method 失效
标题翻译：图像处理器和方法。
公开(公告)号：EP0587443A3
公开(公告)日：1995-06-07
申请号：EP93307166.4
申请日：1993-09-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Masashi , Yamaguchi, Hirohisa
IPC分类号： G11C7/00 , G06F12/02
CPC分类号： G11C7/00 , H04N5/14 , H04N5/907 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/61
摘要： To enable high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operations such as MPEG etc, eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image information can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-bell operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.

5. 发明公开

EP0587443A2 Image processor and method 失效
标题翻译： Bild Prozessor和Verfahren。
公开(公告)号：EP0587443A2
公开(公告)日：1994-03-16
申请号：EP93307166.4
申请日：1993-09-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Masashi , Yamaguchi, Hirohisa
IPC分类号： G11C7/00 , G06F12/02
CPC分类号： G11C7/00 , H04N5/14 , H04N5/907 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/61
摘要： To enable high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operations such as MPEG etc, eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image information can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-bell operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.
摘要翻译：为了以块为单位进行图像信息的高速写入/读取操作，为了完全满足诸如MPEG等的高速操作的需求，八个存储器阵列MA1-MA8并行连接在图像存储单元10中; 因此，在每个存储器阵列MAi中，可以在写入地址生成电路12，存储器阵列控制逻辑14和读取地址生成电路16的控制下，分别写入/读取图像信息。存储器阵列MA1-MA8的输入/输出端子通过输入/输出缓冲器18的八个数据寄存器DREG1-DREG8，选择器电路20的八个行选择器YSEL1-YSEL8和列选择器XSEL以及数据总线22连接到半钟操作电路24。

6. 发明公开

EP0867887A2 Memory access time measurement circuit and method 失效
标题翻译：存储器访问时间测量电路和方法
公开(公告)号：EP0867887A2
公开(公告)日：1998-09-30
申请号：EP98103271.7
申请日：1998-02-25
申请人： Texas Instruments Incorporated
发明人： Hashimoto, Masashi , Hall, James N.
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G01R31/31937 , G11C29/50
摘要： A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry 902 coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store or generate a test data pattern and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or "keeper". For a clock signal having a pulse length or duty cycle that is longer than the access time of the memory circuit, the output of the storage element matches the data pattern stored by the test circuitry. As the clock frequency is increased, or the duty cycle decreased, so that the pulse length approximates the access time, the data output from the storage element no longer matches the data expected by the test circuitry, thus allowing a determination of the access time.
摘要翻译：测量存储器电路访问时间的电路。该电路包括具有输入端子，输出端子和时钟端子的存储元件908。存储元件的输入端子耦合到存储器电路900的输出。时钟信号源906耦合到存储元件的时钟端子和存储器电路的时钟端子。该电路还包括耦合到存储器电路的地址和控制端子以及存储元件的输出端子的测试电路902。测试电路可操作用于存储或生成测试数据模式并将该模式与来自存储元件的数据输出进行比较。在一个实施例中，存储元件是包括与触发器串联耦合的时钟使能反相器的数据锁存器。一个实施例中的触发器是交叉耦合的逆变器存储单元或“保持器”。对于具有比存储器电路的存取时间更长的脉冲长度或占空比的时钟信号，存储元件的输出与测试电路存储的数据模式相匹配。随着时钟频率增加或占空比减小，使得脉冲长度接近访问时间，从存储元件输出的数据不再与测试电路预期的数据相匹配，从而允许确定访问时间。

7. 发明公开

EP0828254A2 Improvements in or relating to semiconductor memory devices 失效
标题翻译：在比利时的Bezug aufAbfühlverstärker的Verbesserungen在Halbleiterspeicheranordnungen
公开(公告)号：EP0828254A2
公开(公告)日：1998-03-11
申请号：EP97306887.7
申请日：1997-09-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Masashi
IPC分类号： G11C7/06
CPC分类号： G11C7/06
摘要： A memory unit 30 is provided with a first and second sense amplifier array 32A and 32B. The storage cells 31 of the memory unit are coupled to both sense amplifier arrays. A control unit 34 is provided which controls the operation of the two sense amplifier arrays. The control unit determines through which sense amplifier array data signals are transferred to and from the storage cells. The sense amplifier array not exchanging signals with the I/O terminals can perform the precharge operations and write-back operations. Synchronous operation of the memory unit and a data processing unit can be maintained by alternating the sense amplifier array performing the current memory access operation.
摘要翻译：存储单元30设置有第一和第二读出放大器阵列32A和32B。存储单元的存储单元31耦合到两个读出放大器阵列。提供控制单元34，其控制两个读出放大器阵列的操作。控制单元确定哪个读出放大器阵列的数据信号被传送到存储单元和从存储单元传送。不与I / O端子交换信号的读出放大器阵列可以执行预充电操作和回写操作。可以通过交替执行当前存储器访问操作的读出放大器阵列来保持存储器单元和数据处理单元的同步操作。

8. 发明公开

EP0655723A1 Digital memory for display system using spatial light modulator 失效
标题翻译：数码相机系统Lichtmodulator。
公开(公告)号：EP0655723A1
公开(公告)日：1995-05-31
申请号：EP94118421.0
申请日：1994-11-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Gove, Robert J. , Urbanus, Paul M. , Sampsell, Jeffrey B. , Doherty, Donald B. , Hashimoto, Masashi
IPC分类号： G09G3/34
CPC分类号： G09G3/34 , G09G3/2018 , G09G3/346 , G09G5/39 , G09G2360/18 , H04N5/7458
摘要： A memory (15) for a digital display system (10) having a spatial light modulator (SLM) (16) that displays data in bit-plane format. The memory (15) has control means (25) for row random access. It also has a set of input registers (31) and two sets of output registers (32), (33). The input registers (31) receive pixel data before it has been processed. The memory (15) delivers this data back to a processor (14) for processing via a first set of output registers (32). After processing, the input registers (31) receive pixel data that has been fully processed and is ready for display. The second set of output registers (33), controlled at their input or output by a bit selector (37), delivers bit-planes of data to the SLM (16).
摘要翻译：一种用于具有以位平面格式显示数据的空间光调制器（SLM）（16）的数字显示系统（10）的存储器（15）。存储器（15）具有用于行随机存取的控制装置（25）。它还具有一组输入寄存器（31）和两组输出寄存器（32），（33）。输入寄存器（31）在处理之前接收像素数据。存储器（15）将该数据传送回处理器（14），以经由第一组输出寄存器（32）进行处理。在处理之后，输入寄存器（31）接收已被完全处理并准备好显示的像素数据。通过位选择器（37）在其输入或输出端控制的第二组输出寄存器（33）将数据的位平面传送到SLM（16）。

9. 发明公开

EP0590591A3 Static random access memory for gate array devices 失效
标题翻译： Statatcher RAM-SpeicherfürGattermatrixvorrichtungen。
公开(公告)号：EP0590591A3
公开(公告)日：1995-03-15
申请号：EP93115622.8
申请日：1993-09-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Masashi
IPC分类号： H03K19/177 , G11C11/412 , H03K3/01 , H01L27/118
CPC分类号： H03K3/012 , G11C11/412
摘要： A gate array device (10) includes a plurality of static random access memory cells (11). Each memory cell (11) comprises n-channel pass gate transistors (12, 14), n-channel drive transistors (16, 18), and p-channel transistors (20, 22). All transistors within the memory cell (11) are approximately of the same size. A resistance element (23) connects to the p-channel transistors (20, 22) in each memory cell (11), generating a new apply voltage ( V ¯ cr ). The resistance element (23) effectively reduces the size of the p-channel transistors (20, 22) to below the size of the drive transistors (16, 18). By effectively reducing the size of the p-channel transistors (20, 22), the speed, accuracy, and stability of the memory cell (11) are enhanced despite the similar sizes of the transistors in the gate array device (10).
摘要翻译：门阵列器件（10）包括多个静态随机存取存储单元（11）。每个存储单元（11）包括n沟道栅极晶体管（12,14），n沟道驱动晶体管（16,18）和p沟道晶体管（20,22）。存储单元（11）内的所有晶体管大致相同的大小。电阻元件（23）连接到每个存储单元（11）中的p沟道晶体管（20,22），产生新的施加电压（Vcr）。电阻元件（23）有效地将p沟道晶体管（20,22）的尺寸减小到低于驱动晶体管（16,18）的尺寸。通过有效地减小p沟道晶体管（20,22）的尺寸，尽管门阵列器件（10）中的晶体管的尺寸相似，但是存储单元（11）的速度，精度和稳定性都得到提高。

10. 发明公开

EP0867887A3 Memory access time measurement circuit and method 失效
标题翻译：方法和装置的存储器存取时间的测量
公开(公告)号：EP0867887A3
公开(公告)日：1998-11-25
申请号：EP98103271.7
申请日：1998-02-25
申请人： Texas Instruments Incorporated
发明人： Hashimoto, Masashi , Hall, James N.
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G01R31/31937 , G11C29/50
摘要： A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry 902 coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store or generate a test data pattern and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or "keeper". For a clock signal having a pulse length or duty cycle that is longer than the access time of the memory circuit, the output of the storage element matches the data pattern stored by the test circuitry. As the clock frequency is increased, or the duty cycle decreased, so that the pulse length approximates the access time, the data output from the storage element no longer matches the data expected by the test circuitry, thus allowing a determination of the access time.

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