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1. 发明公开

EP0681239A3 Fault-tolerant computer system with I/O function capabilities 失效
标题翻译：容错计算机系统的I / O功能的能力。
公开(公告)号：EP0681239A3
公开(公告)日：1996-01-24
申请号：EP95111006.3
申请日：1989-12-08
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Cutts, Richard W., Jr. , Banton, Randall G. , Jewett, Douglas E. , Norwood, Peter C. , Debacker, Kenneth C. , Mehta, Nikhil A. , Allison, John David , Horst, Robert W.
IPC分类号： G06F11/16 , G06F11/18
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F11/0724 , G06F11/0757 , G06F11/1008 , G06F11/1405 , G06F11/1415 , G06F11/1641 , G06F11/1658 , G06F11/1666 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/18 , G06F11/181 , G06F11/182 , G06F11/184 , G06F11/185 , G06F11/20 , G06F11/2015 , G06F11/2017 , G06F2201/85 , G11C29/74
摘要： This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

2. 发明公开

EP0433979A3 Fault-tolerant computer system with/config filesystem 失效
标题翻译：具有/配置FILESYSTEM的容错计算机系统
公开(公告)号：EP0433979A3
公开(公告)日：1993-05-26
申请号：EP90124582.9
申请日：1990-12-18
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Jewett, Douglas E. , Bereiter, Tom , Vetter, Brian , Banton, Randall G. , Cutts, Richard W., Jr. , Westbrook, Donald C. , Fey, Kyran W., Jr. , Pozdro, John , Debacker, Kenneth C. , Mehta, Nikhil A. , Webster, Phil , Aldridge, Dave , Norwood, Peter C.
IPC分类号： G06F11/18 , G06F11/20 , G06F11/14 , G06F1/12 , G06F1/30
CPC分类号： G06F11/181 , G06F1/12 , G06F1/30 , G06F11/0724 , G06F11/0793 , G06F11/1441 , G06F11/1658 , G06F11/1666 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/185 , G06F11/20 , G06F11/2005 , G06F11/2007 , G06F11/2015 , G06F11/2056 , G06F11/22 , G06F11/2736 , G06F17/30238
摘要： A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. The system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical directory in this filesystem contains a file for each component; each file maps to either a hardware component or a software module. The pseudo-filesystem hierarchy is determined during system initialization and is automatically updated whenever the software or hardware configuration changes. The pseudo-filesystem, called /config filesystem herein, is implemented as a Unix filesystem in the Unix filesystem switch. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown.

3. 发明公开

EP0447578A1 Memory management in high-performance fault-tolerant computer system 失效
标题翻译：在einem hochleistenden fehlertolerierenden Rechnersystem的Speicherverwwung。
公开(公告)号：EP0447578A1
公开(公告)日：1991-09-25
申请号：EP90105103.7
申请日：1990-03-19
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Cutts, Richard W., Jr. , Peet, Charles, E., Jr. , Jewett, Douglas E. , Debacker, Kenneth C. , Mehta, Nikhil A. , Allison, John David , Horst, Robert W.
IPC分类号： G06F11/18
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F11/0724 , G06F11/0757 , G06F11/1008 , G06F11/1405 , G06F11/1415 , G06F11/1641 , G06F11/1658 , G06F11/1666 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/18 , G06F11/181 , G06F11/182 , G06F11/184 , G06F11/185 , G06F11/20 , G06F11/2015 , G06F11/2017 , G06F2201/85 , G11C29/74
摘要： A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. Each CPU has its own fast cache and also a local memory not accessible by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernel is kept in local memory. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.
摘要翻译：容错配置的计算机系统使用三个相同的CPU执行相同的指令流，两个相同的自检存储器模块存储相同数据的重复。三个CPU的存储器引用由连接到两个存储器模块中的每一个的三个单独端口的三个单独的总线进行。三个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他CPU之前的事件，直到所有执行该功能的同时; 可以通过确保所有三个CPU在其指令流中的相同点实现中断来同步中断。通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。许多I / O处理器耦合到两个I / O总线。每个CPU都有自己的快速缓存，还有其他CPU不可访问的本地内存。用于该系统的分层虚拟存储器管理装置采用需求寻呼来将最常用的数据保存在本地存储器中，与全局存储器进行页面交换。与磁盘存储器进行页面交换是通过全局内存; 全局内存用作磁盘缓冲区，也可以保存可能需要加载到本地内存的页面。操作系统内核保存在本地内存中。存储器模块中的共享存储空间中包含一个专用写入区域，以允许诸如软件对CPU特有的状态信息进行投票。所有CPU将状态信息写入其专用写入区域，然后所有CPU都会读取所有私有写入区域，以检测中断原因等异常的功能。

4. 发明公开

EP0447576A1 Synchronization of fault-tolerant computer system having multiple processors 失效
标题翻译：同步eine fehlertolerierenden Rechnersystems mit mehreren Prozessoren。
公开(公告)号：EP0447576A1
公开(公告)日：1991-09-25
申请号：EP90105101.1
申请日：1990-03-19
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Cutts, Richard W, Jr. , Jewett, Douglas E. , Southworth, Richard A. , Debacker Kenneth C. , Mehta, Nikhil A. , Allison, John David , Horst, Robert W.
IPC分类号： G06F11/18
CPC分类号： G06F11/185 , G06F11/0724 , G06F11/0757 , G06F11/10 , G06F11/1008 , G06F11/1405 , G06F11/1415 , G06F11/1645 , G06F11/1658 , G06F11/1666 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/182 , G06F11/20 , G06F11/2007 , G06F11/2015 , G06F11/2017 , G06F15/17 , G06F2201/85 , G11C29/74
摘要： A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
摘要翻译：容错配置的计算机系统使用三个相同的CPU执行相同的指令流，两个相同的自检存储器模块存储相同数据的重复。三个CPU的存储器引用由连接到两个存储器模块中的每一个的三个单独端口的三个单独的总线进行。三个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他CPU之前的事件，直到所有执行该功能的同时; 可以通过确保所有三个CPU在其指令流中的相同点实现中断来同步中断。通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。许多I / O处理器耦合到两个I / O总线。

6. 发明公开

EP0447577A1 High-performance computer system with fault-tolerant capability 失效
标题翻译： Hochleistungsrechnersystem mit fehlertoleranterFähigkeit。
公开(公告)号：EP0447577A1
公开(公告)日：1991-09-25
申请号：EP90105102.9
申请日：1990-03-19
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Cutts, Richard W. Jr. , Banton, Randall G. , Jewett, Douglas E. , Norwood, Peter C. , Debacker, Kenneth C. , Mehta, Nikhil A. , Allison, John David , Horst, Robert W.
IPC分类号： G06F11/18
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F11/0724 , G06F11/0757 , G06F11/1008 , G06F11/1405 , G06F11/1415 , G06F11/1641 , G06F11/1658 , G06F11/1666 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/18 , G06F11/181 , G06F11/182 , G06F11/184 , G06F11/185 , G06F11/20 , G06F11/2015 , G06F11/2017 , G06F2201/85 , G11C29/74
摘要： A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.
摘要翻译：容错配置中的计算机系统使用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。多个CPU松动地同步，如通过检测诸如存储器引用的事件，并使其他任何CPU停止，直到所有执行功能同时执行; 中断可以通过确保所有CPU在其指令流中的相同点实现中断来同步。通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。许多I / O处理器耦合到两个I / O总线。 I / O设备通过一对相同（冗余）I / O处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭，即仅在指令控制下重新指定I / O设备的寄存器的地址。

7. 发明公开

EP0372578A2 Memory management in high-performance fault-tolerant computer system 失效
标题翻译：说话者在fehlertolerantem Hochleistungsrechnersystem。
公开(公告)号：EP0372578A2
公开(公告)日：1990-06-13
申请号：EP89122707.6
申请日：1989-12-08
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Cutts, Richard W., Jr. , Peet, Charles E., Jr. , Jewett, Douglas E. , Debacker, Kenneth C. , Mehta, Nikhil A. , Allison, John David , Horst, Robert W.
IPC分类号： G06F11/16 , G06F11/18
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F11/0724 , G06F11/0757 , G06F11/1008 , G06F11/1405 , G06F11/1415 , G06F11/1641 , G06F11/1658 , G06F11/1666 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/18 , G06F11/181 , G06F11/182 , G06F11/184 , G06F11/185 , G06F11/20 , G06F11/2015 , G06F11/2017 , G06F2201/85 , G11C29/74
摘要： A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. Each CPU has its own fast cache and also local memory not accessible by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernel is kept in local memory. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.
摘要翻译：容错配置的计算机系统使用三个相同的CPU执行相同的指令流，两个相同的自检存储器模块存储相同数据的重复。三个CPU的存储器引用由连接到两个存储器模块中的每一个的三个单独端口的三个单独的总线进行。三个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他CPU之前的事件，直到所有执行该功能的同时; 可以通过确保所有三个CPU在其指令流中的相同点实现中断来同步中断。通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。许多I / O处理器耦合到两个I / O总线。每个CPU都有自己的快速缓存，而且其他CPU也无法访问本地内存。用于该系统的分层虚拟存储器管理装置采用需求寻呼来将最常用的数据保存在本地存储器中，与全局存储器进行页面交换。与磁盘存储器进行页面交换是通过全局内存; 全局内存用作磁盘缓冲区，也可以保存可能需要加载到本地内存的页面。操作系统内核保存在本地内存中。存储器模块中的共享存储空间中包含一个专用写入区域，以允许诸如软件对CPU特有的状态信息进行投票。所有CPU将状态信息写入其专用写入区域，然后所有CPU都会读取所有私有写入区域，以检测中断原因等异常的功能。

8. 发明授权

EP0683456B1 Fault-tolerant computer system with online reintegration and shutdown/restart 失效
标题翻译：容错计算机系统在线重新插入和关闭/启动
公开(公告)号：EP0683456B1
公开(公告)日：1998-07-22
申请号：EP95111528.6
申请日：1990-12-18
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Debacker, Kenneth C. , Mehta, Nikhil A. , Webster, Phil , Aldridge, Dave , Norwood, Peter C. , Jewett, Douglas E. , Bereiter, Tom , Vetter, Brian , Banton, Randall G. , Cutts, Richard W., Jr. , Westbrook, Donald C.
IPC分类号： G06F11/14
CPC分类号： G06F11/1441 , G06F11/2015 , G06F11/22

9. 发明公开

EP0372578A3 Memory management in high-performance fault-tolerant computer system 失效
标题翻译：高性能容错计算机系统中的内存管理
公开(公告)号：EP0372578A3
公开(公告)日：1992-01-15
申请号：EP89122707.6
申请日：1989-12-08
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Cutts, Richard W., Jr. , Peet, Charles E., Jr. , Jewett, Douglas E. , Debacker, Kenneth C. , Mehta, Nikhil A. , Allison, John David , Horst, Robert W.
IPC分类号： G06F11/16 , G06F11/18
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F11/0724 , G06F11/0757 , G06F11/1008 , G06F11/1405 , G06F11/1415 , G06F11/1641 , G06F11/1658 , G06F11/1666 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/18 , G06F11/181 , G06F11/182 , G06F11/184 , G06F11/185 , G06F11/20 , G06F11/2015 , G06F11/2017 , G06F2201/85 , G11C29/74
摘要： A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. Each CPU has its own fast cache and also local memory not accessible by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernel is kept in local memory. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.

10. 发明公开

EP0433979A2 Fault-tolerant computer system with/config filesystem 失效
标题翻译： Fehlertolerantes Rechnersystem mit Online-Wiedereinfügungund Abschaltung / Start。
公开(公告)号：EP0433979A2
公开(公告)日：1991-06-26
申请号：EP90124582.9
申请日：1990-12-18
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Jewett, Douglas E. , Bereiter, Tom , Vetter, Brian , Banton, Randall G. , Cutts, Richard W., Jr. , Westbrook, Donald C. , Fey, Kyran W., Jr. , Pozdro, John , Debacker, Kenneth C. , Mehta, Nikhil A. , Webster, Phil , Aldridge, Dave , Norwood, Peter C.
IPC分类号： G06F11/18 , G06F11/20 , G06F11/14 , G06F1/12 , G06F1/30
CPC分类号： G06F11/181 , G06F1/12 , G06F1/30 , G06F11/0724 , G06F11/0793 , G06F11/1441 , G06F11/1658 , G06F11/1666 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/185 , G06F11/20 , G06F11/2005 , G06F11/2007 , G06F11/2015 , G06F11/2056 , G06F11/22 , G06F11/2736 , G06F17/30238
摘要： A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. The system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical directory in this filesystem contains a file for each component; each file maps to either a hardware component or a software module. The pseudo-filesystem hierarchy is determined during system initialization and is automatically updated whenever the software or hardware configuration changes. The pseudo-filesystem, called /config filesystem herein, is implemented as a Unix filesystem in the Unix filesystem switch. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown.
摘要翻译：容错配置中的计算机系统使用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。系统检测CPU和内存模块中的故障，并将故障单元脱机，同时继续使用良好的单元进行操作。故障单元可以更换并重新集成到系统中，无需关闭。计算机系统采用包括电池备份的电源系统，以便在交流电源故障时，系统可以执行有序关机，将状态保存到磁盘。如果交流电源在关机完成时已经恢复，则重新起动程序将恢复停电时存在的状态。该系统采用伪文件系统来动态管理硬件组件。在这个文件系统中显示为标准的层次目录的目录包含每个组件的文件; 每个文件映射到硬件组件或软件模块。伪文件系统层次结构在系统初始化期间确定，并且每当软件或硬件配置更改时自动更新。伪文件系统（这里称为/ config文件系统）在Unix文件系统交换机中被实现为Unix文件系统。多个CPU松动地同步，如通过检测诸如存储器引用的事件，并使其他任何CPU停止，直到所有执行功能同时执行; 中断可以通过确保所有CPU在其指令流中的相同点实现中断来同步。通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。使用两个相同的I / O总线实现I / O功能，每个总线单独地仅耦合到一个存储器模块。许多I / O处理器耦合到两个I / O总线。 I / O设备通过一对相同（冗余）I / O处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭。

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