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1. 发明公开

EP1401105A1 Voltage offset compensation method for time-interleaved multi-path analog-to-digital sigma-delta converters and respective circuit 有权
标题翻译： Offsetspannungskompensationsverfahrenfürparallele zeitverschachtelte Analog-Digitalwandler sowie Schaltungdafür
公开(公告)号：EP1401105A1
公开(公告)日：2004-03-24
申请号：EP02425563.0
申请日：2002-09-17
申请人： Siemens Mobile Communications S.p.A.
发明人： Gatti, Umberto , Malcovati, Piero , Ferragina, Vincenzo , Fornasari, Andrea
IPC分类号： H03M1/10
CPC分类号： H03M3/384 , H03M3/47
摘要： A multi-path time-interleaved analog-to-digital converter (MP-ADC) exploits an additional reference ADC cyclically connected in parallel to each ADC component part to be calibrated of the multi-path ADC, which can be of any kind, in particular sigma-delta, to whom conventional calibration techniques cannot be applied because of its stochastic behaviour. For each ADC component part the algebraic differences between successive digital outputs of the reference ADC and the ADC under calibration are forwarded to an accumulator circuit (13) which integrates them over a given time slot, obtaining a digital word (CH1',...,CH4') proportional to the difference between the offset of the two paths. A digital adder adds up the digital word so obtained to the output of the ADC component part under calibration multiplied by a scale factor which depends on the length of the given time slot. After a reasonable time the voltage offset of each individual path is proportional to the voltage offset of the only reference path, not necessarily zero. Optionally, the outputs of the digital adder are de-scaled by the same scale factor, restoring the original value. The time-interleaved ADC is continuously running and the voltage offset calibration is performed in background without affecting the normal operation (fig.7) .
摘要翻译：多路时间交织的模数转换器（MP-ADC）利用了一个额外的参考ADC，并行地并行地与待校准的多路径ADC的每个ADC组件部分并行地进行校准，该多路径ADC可以是任何类型的，特定的Σ-Δ，由于其随机行为，传统的校准技术不能应用于此。对于每个ADC组件部分，参考ADC和ADC在校准之间的连续数字输出之间的代数差异被转发到累加器电路（13），其在给定时隙上对它们进行积分，获得数字字（CH1'，...），CH4'）与两个路径的偏移之间的差成比例。数字加法器将所获得的数字字相加在校准下的ADC分量部分的输出乘以比例因子，该比例因子取决于给定时隙的长度。在合理的时间之后，每个单独路径的电压偏移量与唯一参考路径的电压偏移成比例，不一定为零。可选地，数字加法器的输出通过相同的比例因子进行缩放，恢复原始值。时间交织的ADC连续运行，并且在背景中执行电压偏移校准，而不影响正常操作（图7）。

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