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1. 发明公开

EP0895283A3 Method of forming multi-level coplanar metal/insulator films using dual damascene with sacreficial flowable oxide 失效
标题翻译：一种用于使用镶嵌工艺可流动Opferoxyd产生共平面的金属/绝缘多层膜过程
公开(公告)号：EP0895283A3
公开(公告)日：2000-05-03
申请号：EP98110307.0
申请日：1998-06-05
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Feldner, Klaus , Grewal, Virinder , Vollmer, Bernd , Schnabel, Rainer Florian
IPC分类号： H01L21/768
CPC分类号： H01L21/76808
摘要： An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer (412,416) and an insulating layer (418) disposed above the underlying device layer. The method includes forming a trench (404,406) in a top surface of the insulating layer (418) such that the trench (404) is positioned over the underlying device layer (416) and separated therefrom by insulating material (418) at a bottom of the trench. The method also includes, depositing flowable oxide (400) over the top surface of the insulating layer (418) and into the trench (404) followed by planarizing the flowable oxide (400) down to about a level of the top surface of the insulating layer (418). Further, the method includes, etching through the flowable oxide (400) within the trench and through insulating material (418) at the bottom of the trench down to the underlying device layer (416) to form a via (508).

2. 发明公开

EP0917187A3 Method of etching aluminium-based layer 审中-公开
标题翻译：用于蚀刻的含铝层的方法
公开(公告)号：EP0917187A3
公开(公告)日：2000-01-26
申请号：EP98120691.5
申请日：1998-11-06
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation , KABUSHIKI KAISHA TOSHIBA
发明人： Spuler, Bruno , Grewal, Virinder , Narita, Masaki , Chi-Hua, Yang
IPC分类号： H01L21/3213 , H01L21/768 , C23F4/00
CPC分类号： H01L21/32136 , C23F4/00 , H01L21/76838
摘要： An Al-based metal layer (10) is formed on the semiconductor body (11) and then coated with a layer (25) of photoresist. A resist pattern is then formed in the layer (25) of photoresist by means of lithography. The resulting semiconductor substrate (21) is placed in the reaction chamber of ICP (Inductively Coupled Plasma) equipment. A mixed gas containing HCl and BCl 3 is introduced into the reaction chamber to etch the metal layer (10) using the photoresist layer (25) as a mask, thereby forming interconnect lines. The etching is effected by Cl ions or Cl active species disassociated from either HCl or BCl 3 . In this etch process, the Cl ions or Cl active species react with the photoresist to thereby form a sidewall protection film (26) consisting of Al 2 O 3 at sidewalls of the lines of interconnect.

3. 发明公开

EP0824269A2 Method for etching an Al metallization by a C12/HC1 based plasma 失效
标题翻译：等离子体中的Verfahren zumÄtzeneiner Al-Metallisierung mit einem auf C12 / HC1 basierendem等离子体
公开(公告)号：EP0824269A2
公开(公告)日：1998-02-18
申请号：EP97305765.6
申请日：1997-07-31
申请人： International Business Machines Corporation , SIEMENS AKTIENGESELLSCHAFT
发明人： Naeem, Munir D. , Burns, Stuart M. , Christie, Rosemary , Grewal, Virinder
IPC分类号： H01L21/3213 , C23F4/00 , H01J37/32
CPC分类号： H01L21/32136 , C23F4/00
摘要： RIE of metallization is achieved at low power and low pressure using Cl 2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl 2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl 2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl 2 and HCl and an inert gas, such as N 2 are controlled in a manner such that a very thin side wall layer (10-100Å) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching. The side wall layer improves the isotropic nature of the etch such that submicron metallization lines with defect free side walls are formed. Hydrogen (H 2 ) can be added to the plasma and will act to reduce corrosion.
摘要翻译：通过使用Cl2和HCl作为反应物种来实现金属化的RIE，其通过产生变压器耦合的等离子体，其功率施加到位于衬底上方和下方的电极，其上被金属化被蚀刻。夹在由例如Ti / TiN制成的阻挡层之间的主体铝或铝合金的三层金属化被蚀刻在三步法中，其中在蚀刻阻挡层期间在等离子体中使用相对较少量的Cl 2并且相对地在大量铝或铝合金层的蚀刻期间使用较高量的Cl 2。蚀刻剂Cl2和HCl以及惰性气体（例如N 2）的比例被控制为使得在RIE期间产生的反应副产物的非常薄的侧壁层（10-100安培）沉积在形成于其中的沟槽的侧壁上蚀刻期间的金属化。侧壁层改善了蚀刻的各向同性，从而形成具有无缺陷侧壁的亚微米金属化线。可以将氢（H2）加入到等离子体中，并且起作用以减少腐蚀。

4. 发明公开

EP0807968A2 Etching a metal silicide with HC1 and chlorine 失效
标题翻译： Ätzeneines Metallsilizids mit HCl and Chlor
公开(公告)号：EP0807968A2
公开(公告)日：1997-11-19
申请号：EP97107458.8
申请日：1997-05-06
申请人： KABUSHIKI KAISHA TOSHIBA , International Business Machines Corporation , SIEMENS AKTIENGESELLSCHAFT
发明人： Hoh, Peter D. , Ohiwa, Tokuhisa , Grewal, Virinder , Spuler, Bruno , Kocon, Waldemar , Wiltshire, Guadalupe
IPC分类号： H01L21/321
CPC分类号： H01L21/32137
摘要： Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl 2 at a volumetric flowrate ratio of HCl:Cl 2 within the range of 3:1 to 5:1.
摘要翻译：在金属硅化物/多晶硅复合材料的干法蚀刻中，用HCl和Cl 2以HCl:Cl2的体积流量比在3:1至5:1的范围内制备的蚀刻气体，以比多晶硅更快的速度除去金属硅化物。

5. 发明公开

EP0917187A2 Method of etching aluminium-based layer 审中-公开
标题翻译： Methode zurÄtzungeiner aluminiumhaltigen Schicht
公开(公告)号：EP0917187A2
公开(公告)日：1999-05-19
申请号：EP98120691.5
申请日：1998-11-06
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation , KABUSHIKI KAISHA TOSHIBA
发明人： Spuler, Bruno , Grewal, Virinder , Narita, Masaki , Chi-Hua, Yang
IPC分类号： H01L21/3213 , H01L21/768
CPC分类号： H01L21/32136 , C23F4/00 , H01L21/76838
摘要： An Al-based metal layer (10) is formed on the semiconductor body (11) and then coated with a layer (25) of photoresist. A resist pattern is then formed in the layer (25) of photoresist by means of lithography. The resulting semiconductor substrate (21) is placed in the reaction chamber of ICP (Inductively Coupled Plasma) equipment. A mixed gas containing HCl and BCl 3 is introduced into the reaction chamber to etch the metal layer (10) using the photoresist layer (25) as a mask, thereby forming interconnect lines. The etching is effected by Cl ions or Cl active species disassociated from either HCl or BCl 3 . In this etch process, the Cl ions or Cl active species react with the photoresist to thereby form a sidewall protection film (26) consisting of Al 2 O 3 at sidewalls of the lines of interconnect.
摘要翻译：在半导体本体（11）上形成Al基金属层（10），然后涂覆有光致抗蚀剂层（25）。然后通过光刻法在光致抗蚀剂的层（25）中形成抗蚀剂图案。将得到的半导体衬底（21）放置在ICP（感应耦合等离子体）设备的反应室中。将含有HCl和BCl 3的混合气体引入到反应室中，以使用光致抗蚀剂层（25）作为掩模蚀刻金属层（10），从而形成互连线。蚀刻由Cl离子或Cl活性物质与HCl或BCl3分离实现。在该蚀刻工艺中，Cl离子或Cl活性物质与光致抗蚀剂反应，从而在互连线的侧壁处形成由Al 2 O 3组成的侧壁保护膜（26）。

6. 发明公开

EP0766301A3 Method of forming self-aligned contact holes using a sacrificial polysilicon layer 失效
标题翻译：一种用于生产使用多晶硅的辅助层自对准接触孔的方法
公开(公告)号：EP0766301A3
公开(公告)日：1998-04-15
申请号：EP96113456.6
申请日：1996-08-21
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Poschenrieder, Bernhard , Grewal, Virinder
IPC分类号： H01L21/768
CPC分类号： H01L21/28
摘要： A method of forming a self-aligned contact hole, in particular a bitline contact, includes steps of first depositing a sacrificial polysilicon layer (4) on a spacer dielectric film (3), and thereafter patterning the polysilicon. The polysilicon layer is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide (6) on the polysilicon layer (4), and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon layer (4) is etched away and the spacer dielectric film (3) is etched to form a self-aligned bitline contact.

7. 发明公开

EP0895283A2 Method of forming multi-level coplanar metal/insulator films using dual damascene with sacreficial flowable oxide 失效
标题翻译：一种用于使用镶嵌工艺可流动Opferoxyd产生共平面的金属/绝缘多层膜过程
公开(公告)号：EP0895283A2
公开(公告)日：1999-02-03
申请号：EP98110307.0
申请日：1998-06-05
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Feldner, Klaus , Grewal, Virinder , Vollmer, Bernd , Schnabel, Rainer Florian
IPC分类号： H01L21/768
CPC分类号： H01L21/76808
摘要： An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying device layer and separated therefrom by insulating material at a bottom of the trench. The method also includes, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Further, the method includes, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying device layer to form a via.
摘要翻译：通过上述一个基板设置在层堆叠进行双镶嵌刻蚀的改进的方法。层堆叠包括下器件层和上绝缘下器件层之上设置的层。该方法包括：在检测所述绝缘层的顶表面上形成沟槽并在沟槽位于下器件层上且通过在所述沟槽的底部的绝缘材料从那里分离。因此，该方法包括，在绝缘层的顶部表面并进入接下来的约绝缘层的顶表面的水平降低到可流动氧化物平坦化所述沟槽中沉积的可流动氧化物。此外，该方法包括，通过在沟槽内的可流动氧化物和通过在沟槽底部的绝缘材料向下到下器件层，以形成通过蚀刻。

8. 发明公开

EP0766301A2 Method of forming self-aligned contact holes using a sacrificial polysilicon layer 失效
标题翻译：一种用于生产使用多晶硅的辅助层自对准接触孔的方法
公开(公告)号：EP0766301A2
公开(公告)日：1997-04-02
申请号：EP96113456.6
申请日：1996-08-21
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Poschenrieder, Bernhard , Grewal, Virinder
IPC分类号： H01L21/768
CPC分类号： H01L21/28
摘要： A method of forming a self-aligned contact hole, in particular a bitline contact, includes steps of first depositing a sacrificial polysilicon layer (4) on a spacer dielectric film (3), and thereafter patterning the polysilicon. The polysilicon layer is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide (6) on the polysilicon layer (4), and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon layer (4) is etched away and the spacer dielectric film (3) is etched to form a self-aligned bitline contact.
摘要翻译：形成自对准接触孔，特别是位线接触，所述的方法包括首先沉积上的间隔物的电介质薄膜 - （3）牺牲多晶硅层（4），并且之后图案化该多晶硅的步骤。多晶硅层是牺牲填充在为位线接触柱。该方法包括另外的多晶硅层（4）上沉积中间的线（MOL）氧化物（6），并通过化学机械抛光（CMP）的MOL氧化物平坦化。那里后，多晶硅层（4）被蚀刻掉和间隔电介质成膜（3）进行蚀刻，以形成自对准的位线接触。

9. 发明授权

EP0807968B1 Etching a metal silicide with HCl and chlorine 失效
标题翻译：蚀刻用HCl和氯的金属硅化物
公开(公告)号：EP0807968B1
公开(公告)日：2005-11-16
申请号：EP97107458.8
申请日：1997-05-06
申请人： KABUSHIKI KAISHA TOSHIBA , International Business Machines Corporation , SIEMENS AKTIENGESELLSCHAFT
发明人： Hoh, Peter D. , Ohiwa, Tokuhisa , Grewal, Virinder , Spuler, Bruno , Kocon, Waldemar , Wiltshire, Guadalupe
IPC分类号： H01L21/321
CPC分类号： H01L21/32137

10. 发明公开

EP0807968A3 Etching a metal silicide with HC1 and chlorine 失效
标题翻译： Ätzeneines Metallsilizids mit HC1 und Chlor
公开(公告)号：EP0807968A3
公开(公告)日：1999-07-28
申请号：EP97107458.8
申请日：1997-05-06
申请人： KABUSHIKI KAISHA TOSHIBA , International Business Machines Corporation , SIEMENS AKTIENGESELLSCHAFT
发明人： Hoh, Peter D. , Ohiwa, Tokuhisa , Grewal, Virinder , Spuler, Bruno , Kocon, Waldemar , Wiltshire, Guadalupe
IPC分类号： H01L21/321
CPC分类号： H01L21/32137
摘要： Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl 2 at a volumetric flowrate ratio of HCl:Cl 2 within the range of 3:1 to 5:1.
摘要翻译：在金属硅化物/多晶硅复合材料的干法蚀刻中，用HCl和Cl 2以HCl:Cl2的体积流量比在3:1至5:1的范围内制备的蚀刻气体，以比多晶硅更快的速度除去金属硅化物。

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