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    • 1. 发明公开
      EP0905771A3 Trench capacitor DRAM cell and method of making the same 审中-公开
    • Trench capacitor DRAM cell and method of making the same
    • 沟槽电容DRAM单元及其制造方法
    • EP0905771A3
    • 2001-10-24
    • EP98115782.9
    • 1998-08-21
    • SIEMENS AKTIENGESELLSCHAFT
    • Scheller, Gerd , Gall, Martin , Stengl, Reinhard Johannes
    • H01L21/8242 , H01L27/108
    • H01L27/10864
    • A memory cell (11), which includes a transistor and a capacitor, for use in a DRAM uses a silicon-filled vertical trench (22) as the capacitor and a vertical transistor superposed over the vertical trench in a silicon chip. An epitaxial layer (98) is formed at the top of the fill in the trench. The epitaxial layer (98) is recrystallized by heating for use as intermediate layer of the vertical transistor. The top surface of the workpiece is now masked so that the epitaxial layer (98) can be removed except where it overlies the polysilicon filled trench. Then over the exposed surface of the remaining mesa (100), there is formed an oxide layer (102) that is suitable for use as the gate dielectric. A polysilicon layer (82) is deposited that serves as word line, followed by a metallic silicide layer (92) as bit line.
    • 用于DRAM中的包括晶体管和电容器的存储器单元（11）使用硅填充的垂直沟槽（22）作为电容器和垂直晶体管叠置在硅芯片中的垂直沟槽之上。 外延层（98）形成在沟槽中填充物的顶部。 外延层（98）通过加热重结晶以用作垂直晶体管的中间层。 工件的顶部表面现在被掩盖，使得外延层（98）可以被除去，除了它覆盖多晶硅填充的沟槽之外。 然后在剩余台面（100）的暴露表面上形成适合用作栅极电介质的氧化物层（102）。 沉积多晶硅层（82）作为字线，接着是金属硅化物层（92）作为位线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明公开
      EP0905624A2 Semiconductor memory having redundancy circuit 审中-公开
    • Semiconductor memory having redundancy circuit
    • 半导体存储器有冗余电路
    • EP0905624A2
    • 1999-03-31
    • EP98117014.5
    • 1998-09-09
    • SIEMENS AKTIENGESELLSCHAFT
    • Pfefferl, Karl-Peter , Gall, Martin
    • G06F11/20
    • G11C29/789 , G11C29/80
    • A memory having an array of memory cells. The array includes a plurality of normal memory cells and a redundant memory cell. A decoder is provided for selecting an addressed one of the normal memory cells in response to an address and a normal condition signal and adapted address the redundant memory cell in response to the address and a fault condition signal. A redundant decoder is provided having an electronically erasable read-only-memory cell. The redundant decoder is adapted to produce the normal condition signal and to convert the normal condition signal into the fault condition signal when such read-only-memory cell is programmed into a fault condition. Each one of the read-only memory cells include a flash memory cell, a ferroelectric memory cell, or other such type of electronically erasable read-only memory cell which is substantially non-volatile and is able to retain its programmed state for a relatively long period of time. With such an arrangement, because the electronically erasable read-only-memory cell is electronically programmable, a defective normal memory cell may be replaced with a redundant memory cell the memory is packaged.
    • 具有一组存储单元的存储器。 阵列包括多个正常存储单元和冗余存储单元。 提供解码器用于响应于地址和正常状态信号选择正常存储器单元中的寻址的存储器单元，并且响应于该地址和故障状态信号对冗余存储器单元进行适配。 提供具有电可擦除只读存储器单元的冗余解码器。 当这种只读存储单元被编程为故障状态时，冗余解码器适于产生正常状态信号并将正常状态信号转换成故障状态信号。 每个只读存储单元包括闪存单元，铁电存储单元或其他这种类型的电可擦除只读存储单元，该电可擦除只读存储单元基本上是非易失性的并且能够将其编程状态保持相对较长 一段的时间。 通过这样的配置，因为电可擦除只读存储单元是电子可编程的，所以有缺陷的正常存储单元可以用存储器封装的冗余存储单元代替。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明公开
      EP0905772A3 Trench capacitor DRAM cell and method of making the same 审中-公开
    • Trench capacitor DRAM cell and method of making the same
    • 有严重电容和其制备方法DRAM单元
    • EP0905772A3
    • 2001-10-24
    • EP98116300.9
    • 1998-08-28
    • SIEMENS AKTIENGESELLSCHAFT
    • Scheller, Gerd , Gall, Martin
    • H01L21/8242 , H01L27/108
    • H01L27/10864
    • A memory cell (11), which includes a transistor and a capacitor, for use in a DRAM uses a silicon-filled vertical trench (22) as the capacitor and a vertical transistor superposed over the vertical trench in a silicon chip. An epitaxial layer (78) is formed at the top of the fill in the trench to impart seed information to the primarily polysilicon silicon fill in the trench so that at least the top portion of the deposited silicon in the trench is monocrystalline. A polysilicon layer (82) is deposited over the top surface of the chip, is apertured over the top of the trench, and has its sidewalls oxidized, this oxide layer (86) serving as gate oxide. The opening is then refilled with epitaxial silicon (88) using the seed information provided by the essentially monocrystalline top layer in the trench in which there is created in operation an inversion layer that serves as the channel of the transistor, and the deposited polysilicon layer (82) serves as the word line. Another silicon layer (36) is deposited over the epitaxial layer to serve as the bit line (52). The source/drain regions (37,34) of the transistor are formed at the merger of the deposited layer with the fill (23) in the trench and the merger with the polysilicon layer (36) that serves as the bit line.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明公开
      EP0905624A3 Semiconductor memory having redundancy circuit 审中-公开
    • Semiconductor memory having redundancy circuit
    • 具有冗余电路的半导体存储器
    • EP0905624A3
    • 1999-09-22
    • EP98117014.5
    • 1998-09-09
    • SIEMENS AKTIENGESELLSCHAFT
    • Pfefferl, Karl-Peter , Gall, Martin
    • G06F11/20
    • G11C29/789 , G11C29/80
    • A memory having an array of memory cells. The array includes a plurality of normal memory cells and a redundant memory cell. A decoder is provided for selecting an addressed one of the normal memory cells in response to an address and a normal condition signal and adapted address the redundant memory cell in response to the address and a fault condition signal. A redundant decoder is provided having an electronically erasable read-only-memory cell. The redundant decoder is adapted to produce the normal condition signal and to convert the normal condition signal into the fault condition signal when such read-only-memory cell is programmed into a fault condition. Each one of the read-only memory cells include a flash memory cell, a ferroelectric memory cell, or other such type of electronically erasable read-only memory cell which is substantially non-volatile and is able to retain its programmed state for a relatively long period of time. With such an arrangement, because the electronically erasable read-only-memory cell is electronically programmable, a defective normal memory cell may be replaced with a redundant memory cell the memory is packaged.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明公开
      EP0905771A2 Trench capacitor DRAM cell and method of making the same 审中-公开
    • Trench capacitor DRAM cell and method of making the same
    • 沟槽电容DRAM单元及其制造方法
    • EP0905771A2
    • 1999-03-31
    • EP98115782.9
    • 1998-08-21
    • SIEMENS AKTIENGESELLSCHAFT
    • Scheller, Gerd , Gall, Martin , Stengl, Reinhard Johannes
    • H01L21/8242 , H01L27/108
    • H01L27/10864
    • A memory cell, which includes a transistor and a capacitor, for use in a DRAM uses a silicon-filled vertical trench as the capacitor and a vertical transistor superposed over the vertical trench in a silicon chip. An epitaxial layer is formed at the top of the fill in the trench to impart seed information to the primarily polysilicon silicon fill in the trench. A polysilicon layer is deposited over the top surface of the chip, is apertured over the top of the trench, and has its sidewalls oxidized. The opening is then refilled with epitaxial silicon in which there is created in operation an inversion layer that serves as the channel of the transistor, and the deposited polysilicon layer serves as the word line. Another silicon layer is deposited over the epitaxial layer to serve as the bit line. The source/drain regions of the transistor are formed at the merger of the deposited layer with the fill in the trench and the merger with the polysilicon layer that serves as the bit line.
    • 用于DRAM中的包括晶体管和电容器的存储器单元使用硅填充的垂直沟槽作为电容器和垂直晶体管叠置在硅芯片中的垂直沟槽之上。 在沟槽中的填充物顶部形成外延层，以将种子信息传递给沟槽中的主要多晶硅填充物。 多晶硅层沉积在芯片的顶部表面上，在沟槽的顶部开孔，并且其侧壁被氧化。 然后用外延硅重新填充开口，其中在操作中产生用作晶体管沟道的反型层，并且沉积的多晶硅层用作字线。 另外的硅层沉积在外延层上以用作位线。 晶体管的源极/漏极区在沉积层与沟槽中的填充物的合并处形成，并且与作为位线的多晶硅层合并。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明公开
      EP0905772A2 Trench capacitor DRAM cell and method of making the same 审中-公开
    • Trench capacitor DRAM cell and method of making the same
    • DRAM Zelle mit Grabenkondensator和Verfahren zu deren Herstellung
    • EP0905772A2
    • 1999-03-31
    • EP98116300.9
    • 1998-08-28
    • SIEMENS AKTIENGESELLSCHAFT
    • Scheller, Gerd , Gall, Martin
    • H01L21/8242 , H01L27/108
    • H01L27/10864
    • A memory cell, which includes a transistor and a capacitor, for use in a DRAM uses a silicon-filled vertical trench as the capacitor and a vertical transistor superposed over the vertical trench in a silicon chip. An epitaxial layer is formed at the top of the fill in the trench to impart seed information to the primarily polysilicon silicon fill in the trench. A polysilicon layer is deposited over the top surface of the chip, is apertured over the top of the trench, and has its sidewalls oxidized. The opening is then refilled with epitaxial silicon in which there is created in operation an inversion layer that serves as the channel of the transistor, and the deposited polysilicon layer serves as the word line. Another silicon layer is deposited over the epitaxial layer to serve as the bit line. The source/drain regions of the transistor are formed at the merger of the deposited layer with the fill in the trench and the merger with the polysilicon layer that serves as the bit line.
    • 包括用于DRAM的晶体管和电容器的存储单元使用硅填充的垂直沟槽作为电容器，并且在硅芯片中叠加在垂直沟槽上的垂直晶体管。 在沟槽中的填充物的顶部形成外延层，以将种子信息提供给沟槽中的主要多晶硅硅填充物。 多晶硅层沉积在芯片的顶表面上，在沟槽的顶部开孔，并且其侧壁被氧化。 然后用外延硅重新填充开口，其中在操作中产生用作晶体管的沟道的反转层，并且沉积的多晶硅层用作字线。 另一硅层沉积在外延层上以用作位线。 晶体管的源极/漏极区域在沉积层与沟槽中的填充物的合并形成并且与用作位线的多晶硅层的合并形成。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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