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1. 发明授权

EP2556507B1 ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS 有权
公开(公告)号：EP2556507B1
公开(公告)日：2018-09-19
申请号：EP11713458.5
申请日：2011-04-05
申请人： Qualcomm Incorporated
发明人： ZHU, Xiaochun , RAO, Hari M. , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659 , G11C11/1693
摘要： Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.

2. 发明公开

EP2556507A1 ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS 审中-公开
标题翻译：不相容的SCHREIBSCHEMAFÜRMAGNETISCHE BITZELLENELEMENTE
公开(公告)号：EP2556507A1
公开(公告)日：2013-02-13
申请号：EP11713458.5
申请日：2011-04-05
申请人： Qualcomm Incorporated
发明人： ZHU, Xiaochun , RAO, Hari M. , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659 , G11C11/1693
摘要： Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.
摘要翻译：不对称切换是针对磁头单元元件定义的。用于存储器和其他器件的磁位单元包括耦合到MTJ结构的晶体管。位线在位单元的一个端子耦合到MTJ结构。在位单元的另一个端子处，源极线耦合到晶体管的源极/漏极端子。位线由提供第一电压的位线驱动器驱动。源极线由提供第二电压的源极线驱动器驱动。第二电压大于第一电压。通过将较高的第二电压施加到源极线和/或降低磁头单元元件中的整体寄生电阻的一个或组合来提高位单元和MTJ结构的开关特性并使其变得更可靠。

3. 发明授权

EP2569772B1 WRITE ENERGY CONSERVATION IN MEMORY 有权
标题翻译： WRITE节能商店
公开(公告)号：EP2569772B1
公开(公告)日：2015-04-01
申请号：EP11721891.7
申请日：2011-05-09
申请人： Qualcomm Incorporated
发明人： RAO, Hari M. , KIM, Jung Pill , KIM, Taehyun , ZHU, Xiaochun , LEE, Kangho , HAO, Wuyang
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1693

4. 发明公开

EP2569772A1 WRITE ENERGY CONSERVATION IN MEMORY 有权
标题翻译： WRITE节能商店
公开(公告)号：EP2569772A1
公开(公告)日：2013-03-20
申请号：EP11721891.7
申请日：2011-05-09
申请人： Qualcomm Incorporated
发明人： RAO, Hari M. , KIM, Jung Pill , KIM, Taehyun , ZHU, Xiaochun , LEE, Kangho , HAO, Wuyang
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1693
摘要： A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the first write signal is generated, and then compares the stored data with the received bits of data to determine whether each of the received bits of data was written to the memory. In response to a second write signal, received bits of data determined not to have been written during the first write signal, are written.

5. 发明授权

EP2569773B1 MEMORY DEVICE HAVING A LOCAL CURRENT SINK 有权
标题翻译：具有本地电流接收器的存储器件
公开(公告)号：EP2569773B1
公开(公告)日：2017-06-14
申请号：EP11724313.9
申请日：2011-05-10
申请人： Qualcomm Incorporated
发明人： KIM, Jung Pill , RAO, Hari M.
IPC分类号： G11C11/16 , G11C13/00 , G11C29/02 , G11C29/12
CPC分类号： G11C29/02 , G11C11/1659 , G11C11/1675 , G11C11/1697 , G11C13/0069 , G11C29/025 , G11C29/12005 , G11C2013/0073 , G11C2013/0078 , G11C2029/1204

6. 发明公开

EP2619765A1 REGISTERS WITH FULL SCAN CAPABILITY 审中-公开
标题翻译：注册全扫描功能
公开(公告)号：EP2619765A1
公开(公告)日：2013-07-31
申请号：EP11771296.8
申请日：2011-09-21
申请人： Qualcomm Incorporated
发明人： RAO, Hari M. , YOON, Sei Seung , CHEN, Nan
IPC分类号： G11C29/32 , G01R31/3185
CPC分类号： G01R31/318541 , G11C11/417 , G11C29/32
摘要： A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.

7. 发明公开

EP2550658A1 MULTI-PORT NON-VOLATILE MEMORY THAT INCLUDES A RESISTIVE MEMORY ELEMENT 审中-公开
标题翻译： NICHTFLÜCHTIGERMULTIPORT-SPEICHER MIT RESISTIVEM SPEICHERELEMENT
公开(公告)号：EP2550658A1
公开(公告)日：2013-01-30
申请号：EP11712122.8
申请日：2011-03-22
申请人： Qualcomm Incorporated
发明人： RAO, Hari M. , KIM, Jung Pill
IPC分类号： G11C8/16 , G11C11/16 , G11C13/00
CPC分类号： G11C11/16 , G06F17/50 , G11C8/16 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/003 , G11C2213/74 , G11C2213/79
摘要： A system and method to access a multi-port non-volatile memory that includes a resistive memory element is disclosed. In a particular embodiment, a multi-port non-volatile memory device is disclosed that includes a resistive memory cell and multiple ports coupled to the resistive memory cell.
摘要翻译：公开了一种用于访问包括电阻性存储器元件的多端口非易失性存储器的系统和方法。在特定实施例中，公开了一种多端口非易失性存储器件，其包括电阻存储器单元和耦合到电阻存储器单元的多个端口。

8. 发明公开

EP2732449A1 MRAM SENSING WITH MAGNETICALLY ANNEALED REFERENCE CELL 有权
标题翻译：具有磁回火参考单元MRAM测量
公开(公告)号：EP2732449A1
公开(公告)日：2014-05-21
申请号：EP12742990.0
申请日：2012-07-11
申请人： Qualcomm Incorporated
发明人： RAO, Hari M. , ZHU, Xiaochun
IPC分类号： G11C11/16 , H01L43/08
CPC分类号： G11C11/1673 , G11C7/14 , G11C11/16 , G11C11/1659 , G11C13/004 , H01L43/12 , Y10T29/49117
摘要： Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation.

9. 发明公开

EP2603918A2 SYSTEM AND METHOD TO INITIATE A HOUSEKEEPING OPERATION AT A MOBILE DEVICE 审中-公开
标题翻译：系统和方法，启动过程功课在移动设备
公开(公告)号：EP2603918A2
公开(公告)日：2013-06-19
申请号：EP11745898.4
申请日：2011-08-12
申请人： Qualcomm Incorporated
发明人： TOMS, Thomas R. , RAO, Hari M. , KANG, Seung H. , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G11C16/30 , G11C5/14 , H04W52/00
CPC分类号： G11C16/3418 , G06F1/263 , G06F11/1048
摘要： A system and method to initiate a housekeeping operation at a mobile device is disclosed. In a particular embodiment, a method at a mobile device includes modifying a scheduled housekeeping operation in response to determining that the mobile device is in a charging mode.

10. 发明公开

EP2550656A1 MULTIPLE INSTRUCTION STREAMS MEMORY SYSTEM 有权
标题翻译： SPEICHERSYSTEM MT MEHREREN BEFEHLSKETTEN
公开(公告)号：EP2550656A1
公开(公告)日：2013-01-30
申请号：EP11713405.6
申请日：2011-03-22
申请人： Qualcomm Incorporated
发明人： RAO, Hari M. , KIM, Jung Pill , HAGHIGHI, Siamack
IPC分类号： G11C8/08 , G11C8/16 , G11C11/16 , G11C13/00
摘要： A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element.
摘要翻译：公开了一种在包括多个非易失性存储器的存储器单元中读取和写入数据的系统和方法。在特定实施例中，公开了一种包括多个存储器单元的存储器件，其中至少一个存储器单元包括第一非易失性存储器，其包括第一电阻存储元件和第二多端口非易失性存储器，包括第二电阻性存储元件。

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