专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3891645A1 REMOTE ENFORCEMENT OF DEVICE MEMORY 审中-公开
公开(公告)号：EP3891645A1
公开(公告)日：2021-10-13
申请号：EP19806293.7
申请日：2019-11-27
申请人： Nagravision S.A.
发明人： GREMAUD, Fabien , FUCHS, Pascal , VILLEGAS, Karine , PERRINE, Jérôme , HAUTIER, Roan
IPC分类号： G06F21/74 , G06F21/78

2. 发明授权

EP3398319B1 METHODS AND SYSTEMS FOR ENCRYPTING COMMUNICATIONS USING A SECURE ELEMENT 有权转让
公开(公告)号：EP3398319B1
公开(公告)日：2020-07-15
申请号：EP17705856.7
申请日：2017-02-16
申请人： Nagravision S.A.
发明人： BENOIT, Bernard , FOURNIER, Jean-Claude , PERRINE, Jérôme , GAUTERON, Laurent
IPC分类号： H04L29/06 , G06F21/60

3. 发明公开

EP3304737A1 METHOD FOR GENERATING A VALUE INHERENT TO AN ELECTRONIC CIRCUIT, ELECTRONIC CIRCUIT GENERATING THIS VALUE AND METHOD FOR USING SUCH A VALUE 有权
标题翻译：用于生成电子电路固有值的方法，生成该值的电子电路和使用该值的方法
公开(公告)号：EP3304737A1
公开(公告)日：2018-04-11
申请号：EP16727355.6
申请日：2016-05-26
申请人： Nagravision S.A.
发明人： MACCHETTI, Marco , HAUTIER, Roan , FAVI, Claudio , PERRINE, Jérôme
IPC分类号： H03K3/84 , H04L9/08
摘要： A method for generating a value inherent to an electronic circuit by measuring a physical quantity carried out on components of the electronic circuit, comprising calculating and associating to each component at least one value derived from a series of measurements carried out on said component, the calculating of the at least one value comprising: determining a statistical value from said series of measurements, defining said value derived from the series of measures as being said statistical value or an uncertainty range calculated from said statistical value, forming a collection of invariable pairs of components, selecting, in said collection, pairs so that said values associated to the components of each one of these pairs are spaced from each other by at least a setpoint value, generating said value inherent to the electronic circuit by concatenating the results of comparisons based on at least one of the values associated to the components of each selected pair, and data among which at least one is derived from these values, said results being processed in an invariable order like said values or data relative to these pairs during said comparisons.

4. 发明授权

EP3304737B1 METHOD FOR GENERATING A VALUE INHERENT TO AN ELECTRONIC CIRCUIT, ELECTRONIC CIRCUIT GENERATING THIS VALUE AND METHOD FOR USING SUCH A VALUE 有权
公开(公告)号：EP3304737B1
公开(公告)日：2020-09-02
申请号：EP16727355.6
申请日：2016-05-26
申请人： Nagravision S.A.
发明人： MACCHETTI, Marco , HAUTIER, Roan , FAVI, Claudio , PERRINE, Jérôme
IPC分类号： H03K3/84 , H04L9/08 , G09C1/00

5. 发明授权

EP2907067B1 METHOD AND SYSTEM FOR SMART CARD CHIP PERSONALIZATION 有权
标题翻译：方法和系统智能卡芯片个人化
公开(公告)号：EP2907067B1
公开(公告)日：2017-01-11
申请号：EP13773769.8
申请日：2013-10-08
申请人： Nagravision S.A.
发明人： HAUTIER, Roan , MACCHETTI, Marco , PERRINE, Jérôme
IPC分类号： G06F21/57 , G06F21/76 , G06F21/31 , G06F21/44 , H04L9/08 , H04L9/14 , H04L9/06
CPC分类号： H04L9/0897 , G06F21/31 , G06F21/44 , G06F21/572 , G06F21/76 , H04L9/0643 , H04L9/0869 , H04L9/0877 , H04L9/14 , H04L2209/24
摘要： A method and system configured for personalizing at least one chip (IC), intended to be integrated into a smart card, comprising a tester (T) associated to a (Field Programmable Gate Array) FPGA device (WB) connected to the chip (IC), the chip (IC) being part of a wafer (W) comprising an arrangement of a plurality of chips and a disposable hardware module (HM) for verifying presence of the chip (IC) on the wafer (W). The tester (T) sends a first secret code (S1) to the FPGA device (WB), which sends a command (C) to the chip to initiate a test mode activation. The FPGA device (WB) encrypts a second secret code (S2) by using a secret encryption algorithm (E) parameterized with a true random number (R) received from the chip (IC) and the first secret code (S1) to obtain a first cryptogram M1 which is sent to the chip (IC). The chip (IC) determines a second cryptogram (M2) by carrying out a Boolean function (F) over a result obtained by decryption of the first cryptogram (M1) using the inverse of the secret encryption algorithm (E -1 ) parameterized with the random number (R) and the first secret code (S1). The second cryptogram (M2) is compared with a calculated result F(S2) obtained by carrying out the Boolean function (F) over the second secret code (S2) temporarily stored on the chip (IC). The FPGA device (WB) performs personalization of the chip (IC) only if the test mode of the chip (IC) is enabled by a successful comparison between the second cryptogram (M2) and the calculated result F(S2).

6. 发明公开

EP3483772A1 INTEGRATED CIRCUIT PERSONALISATION WITH DATA ENCRYPTED WITH THE OUTPUT OF A PHYSICALLY UNCLONABLE FUNCTION 审中-公开
公开(公告)号：EP3483772A1
公开(公告)日：2019-05-15
申请号：EP17201496.1
申请日：2017-11-14
申请人： Nagravision S.A.
发明人： BELLON, Sébastien , FAVI, Claudio , HAUTIER, Roan , MACCHETTI, Marco , PERRINE, Jérôme
IPC分类号： G06F21/72 , G06F21/73 , G06F21/79 , H04L9/32
摘要： An integrated circuit and a method of configuring a plurality of integrated circuits are disclosed. Each integrated circuit comprises a cryptographic key specific to it. Each integrated circuit comprises a cryptographic key specific to it. Each cryptographic key can be generated on the respective integrated circuit using a physical unclonable function and data associated with the cryptographic key, e.g. a configuration message comprising instructions for generating the cryptographic key using the physical unclonable function. The cryptographic key specific to the integrated circuit is not stored on the integrated circuit. Each of the plurality of integrated circuits are configured using a data file that is encrypted with the respective cryptographic key specific to the integrated circuit, circuit.

7. 发明授权

EP3022940B1 METHODE POUR LA PROTECTION DE CLES DE DECHIFFREMENT DANS UN DECODEUR ET DECODEUR POUR LA MISE EN OEUVRE DE CETTE METHODE 无效
公开(公告)号：EP3022940B1
公开(公告)日：2018-09-05
申请号：EP14734841.1
申请日：2014-07-04
申请人： Nagravision S.A.
发明人： MACCHETTI (IT), Marco , PERRINE, Jérôme , SERVET, Patrick , HUNACEK, Didier
IPC分类号： H04N21/4385 , H04N21/4405 , H04N21/4408 , H04N21/4623
CPC分类号： H04N21/4623 , H04N21/43853 , H04N21/4405 , H04N21/4408

8. 发明公开

EP3304850A1 METHODS AND SYSTEMS FOR COMMUNICATION-SESSION ARRANGEMENT ON BEHALF OF CRYPTOGRAPHIC ENDPOINTS 有权
标题翻译：用于表示密码终端的通信 - 会话安排的方法和系统
公开(公告)号：EP3304850A1
公开(公告)日：2018-04-11
申请号：EP16726595.8
申请日：2016-06-03
申请人： Nagravision S.A.
发明人： PERRINE, Jérôme , BENOIT, Bernard , VAN RIEK, Maurice , OSEN, Karl
IPC分类号： H04L29/06 , H04W12/02 , H04M1/253 , H04M1/60
CPC分类号： H04L63/045 , H04L63/0428 , H04L63/061 , H04L65/1006 , H04L65/1069 , H04L65/608 , H04M1/006 , H04M1/2535 , H04M1/6066 , H04W4/80 , H04W12/02
摘要： In an embodiment, a communication device receives a request to establish a media session with a remote endpoint. In response to receiving the request, the communication device exchanges media-session control data with the remote endpoint on behalf of a local endpoint to establish the requested media session between the local endpoint and the remote endpoint. The communication device is communicatively connected to the local endpoint via a Personal Area Network (PAN) communication link. The communication device relays media-session payload data between the local and remote endpoints. The media-session payload data (i) is associated with the media session and (ii) is encrypted based on at least one payload-data cryptographic key that is not accessible to the communication device.

9. 发明公开

EP2907067A1 METHOD AND SYSTEM FOR SMART CARD CHIP PERSONALIZATION 有权
标题翻译： VERFAHREN UND SYSTEM ZUR CHIPPERSONALISIERUNG VON CHIPKARTEN
公开(公告)号：EP2907067A1
公开(公告)日：2015-08-19
申请号：EP13773769.8
申请日：2013-10-08
申请人： Nagravision S.A.
发明人： HAUTIER, Roan , MACCHETTI, Marco , PERRINE, Jérôme
IPC分类号： G06F21/31 , G06F21/44
CPC分类号： H04L9/0897 , G06F21/31 , G06F21/44 , G06F21/572 , G06F21/76 , H04L9/0643 , H04L9/0869 , H04L9/0877 , H04L9/14 , H04L2209/24
摘要： A method and system configured for personalizing at least one chip (IC), intended to be integrated into a smart card, comprising a tester (T) associated to a (Field Programmable Gate Array) FPGA device (WB) connected to the chip (IC), the chip (IC) being part of a wafer (W) comprising an arrangement of a plurality of chips and a disposable hardware module (HM) for verifying presence of the chip (IC) on the wafer (W). The tester (T) sends a first secret code (S1) to the FPGA device (WB), which sends a command (C) to the chip to initiate a test mode activation. The FPGA device (WB) encrypts a second secret code (S2) by using a secret encryption algorithm (E) parameterized with a true random number (R) received from the chip (IC) and the first secret code (S1) to obtain a first cryptogram M1 which is sent to the chip (IC). The chip (IC) determines a second cryptogram (M2) by carrying out a Boolean function (F) over a result obtained by decryption of the first cryptogram (M1) using the inverse of the secret encryption algorithm (E -1 ) parameterized with the random number (R) and the first secret code (S1). The second cryptogram (M2) is compared with a calculated result F(S2) obtained by carrying out the Boolean function (F) over the second secret code (S2) temporarily stored on the chip (IC). The FPGA device (WB) performs personalization of the chip (IC) only if the test mode of the chip (IC) is enabled by a successful comparison between the second cryptogram (M2) and the calculated result F(S2).
摘要翻译：一种方法和系统，被配置为个性化旨在被集成到智能卡中的至少一个芯片（IC），包括与连接到芯片（IC）的（现场可编程门阵列）FPGA器件（WB）相关联的测试器（T）），所述芯片（IC）是包括多个芯片的布置的晶片（W）的一部分，以及用于验证晶片（W）上的芯片（IC）的存在的一次性硬件模块（HM）。测试器（T）向FPGA器件（WB）发送第一密码（S1），该器件向芯片发送命令（C）以启动测试模式激活。 FPGA设备（WB）通过使用从芯片（IC）和第一密码（S1）接收的真随机数（R）参数化的秘密加密算法（E）来加密第二密码（S2），以获得第一密封件M1被发送到芯片（IC）。芯片（IC）通过使用使用参数化的秘密加密算法（E-1）的倒数对第一密文（M1）进行解密获得的结果执行布尔函数（F）来确定第二密码（M2）随机数（R）和第一密码（S1）。将第二密码（M2）与通过临时存储在芯片（IC）上的第二密码（S2）执行布尔函数（F）而获得的计算结果F（S2）进行比较。仅当通过第二密封（M2）和计算结果F（S2）之间的成功比较来启用芯片（IC）的测试模式时，FPGA器件（WB）才执行芯片（IC）的个性化。

10. 发明授权

EP3304849B1 SYSTEMS AND METHODS FOR CONDUCTING SECURE VOIP MULTI-PARTY CALLS 有权转让
公开(公告)号：EP3304849B1
公开(公告)日：2019-07-24
申请号：EP16725843.3
申请日：2016-05-27
申请人： Nagravision S.A.
发明人： FER, François , MACCHETTI, Marco , GAUTERON, Laurent , PERRINE, Jérôme
IPC分类号： H04M7/00 , H04W12/04 , H04W12/08 , G06F16/22 , H04L29/06

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式