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1. 发明授权

EP2023558B1 Radio communication apparatus, radio communication system and radio communication method 有权
标题翻译：装置，系统和方法用于无线通信
公开(公告)号：EP2023558B1
公开(公告)日：2015-06-10
申请号：EP07741842.4
申请日：2007-04-18
申请人： NEC Corporation , NEC Engineering, Ltd.
发明人： SASAKI, Eisaku , SOUMA, Kazuhito
IPC分类号： H04L27/00 , H04B7/26 , H04L1/00
CPC分类号： H04W52/262 , H04L1/0003 , H04L1/0026 , H04L27/0008

2. 发明公开

EP2023558A1 WIRELESS COMMUNICATION DEVCE, WIRELESS COMMUNICATION SYSTEM AND WIRELESS COMMUNICATION METHOD 有权
标题翻译： Vorrichtung，System und Verfahren zur drahtlosen Kommunikation
公开(公告)号：EP2023558A1
公开(公告)日：2009-02-11
申请号：EP07741842.4
申请日：2007-04-18
申请人： NEC Corporation , NEC Engineering, Ltd.
发明人： SASAKI, Eisaku , SOUMA, Kazuhito
IPC分类号： H04L27/00 , H04B7/26
CPC分类号： H04W52/262 , H04L1/0003 , H04L1/0026 , H04L27/0008
摘要： There are provided a radio communication apparatus, a radio communication system, and a radio communication method in which by appropriately conducting control of the ATPC and the adaptive modulation scheme in the continuous signal transmission scheme, a probability of the short break of a signal having high priority can be lowered while reducing a degree of interference in the ordinary state.
A radio communication apparatus for conducting radio communication with another radio communication apparatus by transmission of continuous signals, comprising control means for conducting modulation scheme changeover control to change a modulation scheme according to a state of a transmission path and automatic transmitter power control to control a transmission level of another radio communication apparatus to set a reception level of a reception signal to be received by the own apparatus to a predetermined value, wherein the control means controls, in a situation in which a changeover is conducted from a first modulation scheme to a second modulation scheme under the modulation scheme changeover control, to keep the transmission level of another radio communication apparatus at a predetermined value under the automatic transmitter power control and conducts, in a situation in which resetting is conducted from the second modulation scheme to the first modulation scheme under the modulation scheme changeover control, at least one of transmission level reduction control to stepwise lower by a predetermined value the transmission level kept at the predetermined value under the automatic transmitter power control and reception level confirmation control to confirm a state of the reception level for a fixed period of time.
摘要翻译：提供了一种无线电通信装置，无线电通信系统和无线通信方法，其中通过在连续信号传输方案中适当地进行ATPC和自适应调制方案的控制，具有高信号的短暂断裂的概率可以降低优先级，同时降低普通状态下的干扰程度。一种无线电通信装置，用于通过发送连续信号与另一无线电通信装置进行无线电通信，包括用于进行调制方式切换控制的控制装置，以根据传输路径的状态和自动发射机功率控制改变调制方案以控制传输将另一无线电通信装置的电平设置为将要由本装置接收的接收信号的接收电平设定为预定值，其中控制装置在从第一调制方式切换到第二调制方式的情况下，在调制方式切换控制下的调制方式，在自动发送机功率控制下将另一无线通信装置的发送电平保持在预定值，并且在从第二调制方式进行复位到第一调制方案的情况下进行在modu下发送方式转换控制，在自动发送功率控制和接收电平确认控制下将发送电平降低控制中的至少一个逐步降低预定值的传输电平保持在预定值，以确认固定的接收电平的状态一段的时间。

3. 发明公开

EP3096500A1 COMMUNICATION APPARATUS, DEMODULATION APPARATUS, CARRIER REPRODUCTION APPARATUS, PHASE ERROR COMPENSATION APPARATUS, PHASE ERROR COMPENSATION METHOD, AND STORAGE MEDIUM ON WHICH PHASE ERROR COMPENSATION PROGRAM HAS BEEN STORED 有权
标题翻译：通信设备中，解调，TANK再生装置中，相位误差补偿装置中，相位误差补偿的方法和其上具有相位误差补偿PROGRAM存储在存储设备
公开(公告)号：EP3096500A1
公开(公告)日：2016-11-23
申请号：EP15737729.2
申请日：2015-01-15
申请人： NEC Corporation
发明人： KAMIYA, Norifumi , SASAKI, Eisaku
IPC分类号： H04L27/38
CPC分类号： H04L27/3872 , H04L27/0014 , H04L2027/0067
摘要： [Problem] To enable a large-capacity, high-quality data communication that is excellent in bit error rate characteristic even in an adverse noise environment mainly caused by phase noises or thermal noises. [Solution] Included are: a first phase error detection filter that generates, on the basis of a forward sequence of received symbols, a first phase difference value and a first phase error estimated value; a second phase error detection filter that generates, on the basis of a backward sequence of received symbols, a second phase difference value and a second phase error estimated value; a phase error combination means that generates a third phase error estimated value on the basis of the first and second phase error estimated values and one of the first and second phase difference values; and a phase error compensation means that compensates the phase error of the received symbols in accordance with the third phase error estimated value.
摘要翻译： [问题]为了实现大容量，高质量的数据通信做，即使在不利的由相位噪声或热噪声主要是由于噪声环境具有优良的位误码率特性。 [解决方法]包含有：一第一相位误差检测滤波器做基因率，接收到的符号，第一相位差值和第一相位误差估计值的正向序列的基础上; 第二相位误差检测滤波器做基因率，接收到的符号，第二相位差值和第二相位误差估计值的向后序列的基础上; 相位误差组合bedeutet，DASS基因率三分之一的相位误差估计值的第一和第二相位误差的估计值的基础上和在第一和第二相位差值中的一个上; 和相位误差补偿bedeutet，DASS补偿所接收到的符号的雅舞蹈的相位误差与第三相位误差估计值。

4. 发明公开

EP2843896A1 CARRIER WAVE REPRODUCTION DEVICE AND CARRIER WAVE REPRODUCTION METHOD 有权
标题翻译：载波再现装置和载波再现方法
公开(公告)号：EP2843896A1
公开(公告)日：2015-03-04
申请号：EP13780986.9
申请日：2013-04-23
申请人： NEC Corporation
发明人： KAMIYA, Norifumi , SASAKI, Eisaku
IPC分类号： H04L27/38
CPC分类号： H04L1/0036 , H04L1/0045 , H04L27/0014 , H04L27/22 , H04L27/3818 , H04L27/3836 , H04L2027/0024 , H04L2027/0046 , H04L2027/0061 , H04L2027/0067 , H04L2027/0087
摘要： The present invention provides a carrier wave reproduction device in which bit-error characteristics are improved without decreasing transmission capacity. The carrier wave reproduction device is equipped with an interpolation filter that estimates a phase error for a received symbol on the basis of a pilot symbol included in the received symbol, a first phase rotation machine that rotates a phase of the received symbol in response to the phase error estimated by the interpolation filter and then outputs the rotated symbol as a first output symbol, a phase error compensating unit that compensates for the phase error remaining in the first output symbol and then outputs the result of the compensation as a second output symbol, a QAM symbol demapping unit that calculates both a first bit string corresponding to the first output symbol and a second bit string corresponding to the second output signal, and an error correction decoder which performs error correction on the bit error in the first bit string and outputs the result. The phase error compensating unit refers to the first bit string after error correction has been performed thereon and then compensates for the phase error remaining in the first output symbol.
摘要翻译：本发明提供了一种载波再现装置，其中在不降低传输容量的情况下改善了误码特性。载波再现设备配备有内插滤波器，第一相位旋转机器和第二相位旋转机器，内插滤波器基于包括在接收到的符号中的导频符号来估计接收到的符号的相位误差，第一相位旋转机器响应于然后输出旋转后的符号作为第一输出符号;相位误差补偿单元，补偿第一输出符号中剩余的相位误差，然后输出补偿结果作为第二输出符号; QAM符号解映射单元，其计算对应于第一输出符号的第一比特串和对应于第二输出信号的第二比特串;以及纠错解码器，其对第一比特串中的比特误差进行纠错并输出结果。相位误差补偿单元参考在其上执行了纠错之后的第一位串，然后补偿第一输出符号中剩余的相位误差。

5. 发明公开

EP2645660A1 PLL CIRCUIT 有权
标题翻译： PLL-SCHALTUNG
公开(公告)号：EP2645660A1
公开(公告)日：2013-10-02
申请号：EP11843405.9
申请日：2011-09-20
申请人： NEC Corporation
发明人： SASAKI, Eisaku
IPC分类号： H04L27/38 , H03L7/08 , H03L7/093
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/091 , H04L27/0014 , H04L27/38 , H04L2027/0067
摘要： A PLL circuit, for extracting phase error information from a demodulated signal in which a variance of a phase or an amplitude changes depending on a signal-to-noise power ratio, and providing negative feedback control, to thereby suppress a phase error of the demodulated signal, includes: a phase error detector for producing a phase error signal corresponding to a value of the phase error as the phase error information; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing a control signal based on the limited phase error signal to determine frequency characteristics.
摘要翻译：一种PLL电路，用于从相位或幅度的方差根据信噪比功率比而变化的解调信号中提取相位误差信息，并提供负反馈控制，从而抑制解调后的相位误差信号包括：相位误差检测器，用于产生与相位误差值相对应的相位误差信号作为相位误差信息; 限制电路，用于将相位误差信号的表达范围限制在一定值以下，以产生有限的相位误差信号; 以及环路滤波器，用于基于有限相位误差信号产生控制信号以确定频率特性。

6. 发明公开

EP1137231A1 DEMODULATOR FOR PROCESSING DIGITAL SIGNAL 有权
标题翻译：平行FIR滤波器SOWIE SOLCHE滤波器ENTHALTENDE DEMODULATOREN ZUR VERARBEITUNG EINES DIGITALEN SIGNALS
公开(公告)号：EP1137231A1
公开(公告)日：2001-09-26
申请号：EP00964665.4
申请日：2000-10-04
申请人： NEC Corporation
发明人： SASAKI, Eisaku
IPC分类号： H04L27/22
CPC分类号： H04L27/22 , H04L27/2273 , H04L2027/0057 , H04L2027/0067 , H04L2027/0069
摘要： The serial data signal obtained by carrying out an A/D conversion at two times the modulation speed is S/P-converted, at a data ratio of 1:2, into a pair of parallel data signals of the modulation speed. The demodulation process is carried out by parallelly processing the pair of parallel data signals, resulting in that the demodulation speed is equal to the modulation speed. The serial data obtained by carrying out the A/D conversion at four times the modulation speed is S/P-converted at a data ratio of 1:4, and is then similarly subjected to demodulation at the demodulation speed equal to the modulation speed. With this arrangement, the demodulator carrying out the digital signal processing can be applied to communication systems having a high modulation speed.
摘要翻译：通过以调制速度的两倍进行A / D转换而获得的串行数据信号以1：2的数据比率被S / P转换为调制速度的一对并行数据信号。通过并行处理该对并行数据信号来进行解调处理，导致解调速度等于调制速度。通过以调制速度的四倍进行A / D转换而获得的串行数据以1：4的数据比进行S / P转换，然后类似地以等于调制速度的解调速度进行解调。利用这种布置，执行数字信号处理的解调器可以应用于具有高调制速度的通信系统。

7. 发明授权

EP2645660B1 PLL CIRCUIT 有权
标题翻译： PLL电路
公开(公告)号：EP2645660B1
公开(公告)日：2015-06-10
申请号：EP11843405.9
申请日：2011-09-20
申请人： NEC Corporation
发明人： SASAKI, Eisaku
IPC分类号： H04L27/38 , H03L7/08 , H03L7/093 , H03L7/091 , H04L27/00
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/091 , H04L27/0014 , H04L27/38 , H04L2027/0067

8. 发明公开

EP2066065A1 CHANNEL SWITCH SIGNAL OUTPUTTING CIRCUIT AND CHANNEL SWITCH SIGNAL OUTPUTTING METHOD 审中-公开
标题翻译： KANALSCHALTUNGS-SIGNALAUSGABE-SCHALTKREIS UND KANALSCHALTUNGS-SIGNALAUSGABEVERFAHREN
公开(公告)号：EP2066065A1
公开(公告)日：2009-06-03
申请号：EP07828304.1
申请日：2007-09-21
申请人： NEC Corporation
发明人： SASAKI, Eisaku
IPC分类号： H04L1/22 , H03M13/19
CPC分类号： B23B5/166 , H03M13/1128 , H03M13/2975 , H03M13/353 , H03M13/6337 , Y10T29/49748 , Y10T29/51 , Y10T409/304256
摘要： An error correction decoder (101) counts the number of times of iterative decoding executed in the process of a predetermined error correcting operation, and outputs the iterative decoding count to an averaging circuit (102). The averaging circuit (102) calculates the average value of the iterative decoding counts input from the error correction decoder (101), and outputs the calculated average value of the iterative decoding counts to a comparator (103). The comparator (103) determines whether the iterative decoding count average value is larger than a predetermined threshold value. When determining that the average value is larger than the predetermined threshold value, the comparator (103) determines that a channel switching condition is met, and outputs a channel switching signal to a channel switching circuit (405). This makes it possible to output the channel switching signal under appropriate conditions without increasing the number of circuits in a wireless communication system using a highly coding gain code to be iteratively decoded.
摘要翻译：纠错解码器（101）对在预定纠错操作的处理中执行的迭代解码的次数进行计数，并将迭代解码计数输出到平均电路（102）。平均电路（102）计算从纠错解码器（101）输入的迭代解码计数的平均值，并将计算出的迭代解码计数的平均值输出到比较器（103）。比较器（103）确定迭代解码计数平均值是否大于预定阈值。当确定平均值大于预定阈值时，比较器（103）确定满足通道切换条件，并将通道切换信号输出到通道切换电路（405）。这使得可以在适当的条件下输出信道切换信号，而不需要使用要重复解码的高度编码增益码来增加无线通信系统中的电路数量。

9. 发明公开

EP1936904A1 LOGARITHMIC LIKELIHOOD RATIO CALCULATING CIRCUIT, TRANSMITTER APPARATUS, LOGARITHMIC LIKELIHOOD RATIO CALCULATING METHOD AND PROGRAM 审中-公开
标题翻译：标签：VERHÄLTNISBERECHNUNGSSCHALTUNG，SENDEBZW EMPFANGSVORRICHTUNG，LOGARITHMUSHAFTESVERHÄLTNISBERECHNUNGSVERFAHRENUND PROGRAMM
公开(公告)号：EP1936904A1
公开(公告)日：2008-06-25
申请号：EP07828667.1
申请日：2007-09-28
申请人： NEC Corporation
发明人： SASAKI, Eisaku
IPC分类号： H04L27/38
CPC分类号： H04L25/067 , H04L27/38
摘要： [Problems] To realize a log likelihood ratio calculation performed at a higher speed while the circuit size and the power consumption are reduced, regardless of the multilevel number of a modulation method. [Means for Solving the Problems] A hard-decision bit of the bits indicating the P-axial coordinate of a reception signal point is input to an area detection circuit, and based on the hard-decision bit input, the area detection circuit detects and outputs an area on the phase plane where the coordinate of the reception signal point is present. A soft-decision bit of the bits indicating the coordinate of the reception signal point is input to an LLR circuit, and based on the soft-decision bit input, the LLR circuit calculates a primary LLR. An LLR converter calculates the final LLR based on an output (area detection result) from the area detection circuit. With this configuration, a log likelihood ratio is calculated while limiting the scope, within which the value of the log likelihood ratio varies corresponding to the position of the reception signal point, to a range between adjacent signal points including the hard-decision threshold of the bit.
摘要翻译： [问题]为了实现在电路尺寸和功耗降低的同时以更高的速度执行的对数似然比计算，而不管调制方法的多级数。解决问题的手段将指示接收信号点的P轴坐标的比特的硬判决位输入到区域检测电路，并且基于硬判定比特输入，区域检测电路检测和输出存在接收信号点的坐标的相平面上的区域。指示接收信号点的坐标的位的软判决位被输入到LLR电路，并且基于软判决位输入，LLR电路计算主LLR。 LLR转换器基于来自区域检测电路的输出（区域检测结果）计算最终的LLR。利用该配置，计算对数似然比，同时将对数似然比的值对应于接收信号点的位置变化的范围限制在包括硬判决阈值的相邻信号点之间的范围位。

10. 发明授权

EP2843896B1 CARRIER WAVE REPRODUCTION DEVICE AND CARRIER WAVE REPRODUCTION METHOD 有权
标题翻译：载波再现装置和载波再现方法
公开(公告)号：EP2843896B1
公开(公告)日：2018-04-04
申请号：EP13780986.9
申请日：2013-04-23
申请人： NEC Corporation
发明人： KAMIYA, Norifumi , SASAKI, Eisaku
IPC分类号： H04L27/38 , H04L1/00 , H04L27/00 , H04L27/22
CPC分类号： H04L1/0036 , H04L1/0045 , H04L27/0014 , H04L27/22 , H04L27/3818 , H04L27/3836 , H04L2027/0024 , H04L2027/0046 , H04L2027/0061 , H04L2027/0067 , H04L2027/0087
摘要： The present invention provides a carrier wave reproduction device in which bit-error characteristics are improved without decreasing transmission capacity. The carrier wave reproduction device is equipped with an interpolation filter that estimates a phase error for a received symbol on the basis of a pilot symbol included in the received symbol, a first phase rotation machine that rotates a phase of the received symbol in response to the phase error estimated by the interpolation filter and then outputs the rotated symbol as a first output symbol, a phase error compensating unit that compensates for the phase error remaining in the first output symbol and then outputs the result of the compensation as a second output symbol, a QAM symbol demapping unit that calculates both a first bit string corresponding to the first output symbol and a second bit string corresponding to the second output signal, and an error correction decoder which performs error correction on the bit error in the first bit string and outputs the result. The phase error compensating unit refers to the first bit string after error correction has been performed thereon and then compensates for the phase error remaining in the first output symbol.

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