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1. 发明公开

EP0459521A3 Semiconductor memory device with a redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：EP0459521A3
公开(公告)日：1992-11-19
申请号：EP91108972.0
申请日：1991-05-31
申请人： NEC CORPORATION
发明人： Ohno, Kazuki, c/o NEC Corporation , Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G06F11/20 , G11C29/00
CPC分类号： G11C29/84 , G11C29/86
摘要： In the redundancy circuit, there is provided a data-transfer path switching circuit for switching by path-switching signals paths on which data is transferred from the data-storage places of the write shift register through the memory cell array to the data-storage place. Path switching signals are generated as by blowing the fuse link corresponding to the number of data pieces input into the write shift register. The construction that the data to be read out firstly is transferred to the last data-storage place of the output circuit brings speed-up of readout without shifting previously to readout when a shift register is used as output circuit. With a data register as output circuit, the output control circuit is fixed, with an effect of making trouble-some decoder switching unnecessary.

2. 发明公开

EP0481494A2 Memory apparatus 失效
标题翻译： Speicheranordnung。
公开(公告)号：EP0481494A2
公开(公告)日：1992-04-22
申请号：EP91117760.8
申请日：1991-10-17
申请人： NEC CORPORATION
发明人： Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G11C7/00
CPC分类号： G11C7/1072
摘要： A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.
摘要翻译：存储装置包括用于存储数据的存储单元阵列，用于接收要存储在存储单元阵列中的输入串行数据并提供要从存储单元阵列读取的输出串行数据的移位寄存器，以及用于在移位寄存器和存储单元阵列之间并行传送数据。在移位寄存器中，输入串行数据被移位到其输出侧，直到第一位到达其最后一步。然后，输入串行数据被传送到存储单元阵列中，由传输门。因此，当存储的数据被读出时，甚至即使在移位寄存器比输入的串行数据长的情况下也不会在开始时提供无效的位。

3. 发明公开

EP0454162A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0454162A2
公开(公告)日：1991-10-30
申请号：EP91106845.0
申请日：1991-04-26
申请人： NEC CORPORATION
发明人： Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C11/4096
摘要： The semiconductor memory device according to the present invention includes a plurality of memory cells that are provided in array form and a plurality of bit lines and word lines that are respectively connected to these memory cells, and comprises a memory cell array arranged so as to form pairs of bit lines, a data register circuit consisting of a plurality of registers, and selection means for respectively connecting predetermined bit line pairs out of the plurality of bit line pairs to a plurality of registers in response to a control signal.
This data register circuit is formed by arranging the plurality of registers in a single line.
With such a constitution, the number of registers that constitute the data register circuit can be reduced compared with the conventional device. Accordingly, it becomes possible to arrange the registers in a single line, the area for the data register circuit can sharply be reduced in comparison to the case of the conventional device, contributing to the integration of the semiconductor memory device.
摘要翻译：根据本发明的半导体存储器件包括以阵列形式提供的多个存储器单元和分别连接到这些存储器单元的多个位线和字线，并且包括布置成形成的存储单元阵列位线对，由多个寄存器组成的数据寄存器电路，以及用于响应于控制信号将多个位线对中的预定位线对分别连接到多个寄存器的选择装置。该数据寄存器电路通过将多个寄存器布置在一条线中而形成。通过这样的结构，与传统的装置相比，可以减少构成数据寄存器电路的寄存器的数量。因此，与现有器件的情况相比，可以将寄存器排列成一行，数据寄存器电路的面积可以大大降低，有助于半导体存储器件的集成。

4. 发明授权

EP0481494B1 Memory apparatus 失效
标题翻译：记忆装置
公开(公告)号：EP0481494B1
公开(公告)日：1997-09-03
申请号：EP91117760.8
申请日：1991-10-17
申请人： NEC CORPORATION
发明人： Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G11C7/00
CPC分类号： G11C7/1072

5. 发明授权

EP0454162B1 Semiconductor memory device 失效
公开(公告)号：EP0454162B1
公开(公告)日：1996-09-25
申请号：EP91106845.0
申请日：1991-04-26
申请人： NEC CORPORATION
发明人： Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C11/4096

6. 发明公开

EP0459521A2 Semiconductor memory device with a redundancy circuit 失效
标题翻译： Halbleiterspeichervorrichtung mit Redundanzschaltung。
公开(公告)号：EP0459521A2
公开(公告)日：1991-12-04
申请号：EP91108972.0
申请日：1991-05-31
申请人： NEC CORPORATION
发明人： Ohno, Kazuki, c/o NEC Corporation , Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G06F11/20 , G11C29/00
CPC分类号： G11C29/84 , G11C29/86
摘要： In the redundancy circuit, there is provided a data-transfer path switching circuit for switching by path-switching signals paths on which data is transferred from the data-storage places of the write shift register through the memory cell array to the data-storage place. Path switching signals are generated as by blowing the fuse link corresponding to the number of data pieces input into the write shift register.
The construction that the data to be read out firstly is transferred to the last data-storage place of the output circuit brings speed-up of readout without shifting previously to readout when a shift register is used as output circuit. With a data register as output circuit, the output control circuit is fixed, with an effect of making trouble-some decoder switching unnecessary.
摘要翻译：在冗余电路中，提供了一种数据传输路径切换电路，用于通过路径切换信号将数据从数据存储位置通过存储单元阵列传送到数据存储位置。通过对与输入到写入移位寄存器的数据片段的数量相对应的熔丝链进行吹送来生成路径切换信号。首先要读出的数据被传送到输出电路的最后数据存储位置的结构使得当使用移位寄存器作为输出电路时，读出的加速不需要先前转移到读出。使用数据寄存器作为输出电路，输出控制电路是固定的，具有不必要的解码器切换的麻烦。

7. 发明授权

EP0459521B1 Semiconductor memory device with a redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：EP0459521B1
公开(公告)日：1997-03-12
申请号：EP91108972.0
申请日：1991-05-31
申请人： NEC CORPORATION
发明人： Ohno, Kazuki, c/o NEC Corporation , Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G06F11/20 , G11C29/00
CPC分类号： G11C29/84 , G11C29/86

8. 发明公开

EP0481494A3 Memory apparatus 失效
标题翻译：记忆装置
公开(公告)号：EP0481494A3
公开(公告)日：1994-12-14
申请号：EP91117760.8
申请日：1991-10-17
申请人： NEC CORPORATION
发明人： Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G11C7/00
CPC分类号： G11C7/1072
摘要： A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.
摘要翻译：一种存储装置包括：存储单元阵列，用于存储数据;移位寄存器，用于接收待存储在存储单元阵列中的输入串行数据，并提供要从存储单元阵列读取的输出串行数据;以及传送门，在移位寄存器和存储单元阵列之间并行传送数据。在移位寄存器中，输入串行数据被移位到其输出侧，直到第一位达到其最后一步。然后，输入串行数据被传输门传输以存储在存储单元阵列中。因此，即使在移位寄存器比输入串行数据长的情况下，即使在开始时刻，当存储的数据被读出时，也不会提供无效位。

9. 发明公开

EP0454162A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0454162A3
公开(公告)日：1993-02-03
申请号：EP91106845.0
申请日：1991-04-26
申请人： NEC CORPORATION
发明人： Hoshino, Yasuharu, c/o NEC Corporation
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C11/4096
摘要： The semiconductor memory device according to the present invention includes a plurality of memory cells that are provided in array form and a plurality of bit lines and word lines that are respectively connected to these memory cells, and comprises a memory cell array arranged so as to form pairs of bit lines, a data register circuit consisting of a plurality of registers, and selection means for respectively connecting predetermined bit line pairs out of the plurality of bit line pairs to a plurality of registers in response to a control signal. This data register circuit is formed by arranging the plurality of registers in a single line. With such a constitution, the number of registers that constitute the data register circuit can be reduced compared with the conventional device. Accordingly, it becomes possible to arrange the registers in a single line, the area for the data register circuit can sharply be reduced in comparison to the case of the conventional device, contributing to the integration of the semiconductor memory device.
摘要翻译：根据本发明的半导体存储器件包括以阵列形式提供的多个存储器单元以及分别连接到这些存储器单元的多个位线和字线，并且包括存储器单元阵列，该存储器单元阵列布置成形成成对的位线，由多个寄存器组成的数据寄存器电路，以及用于响应于控制信号将多个位线对中的预定位线对分别连接到多个寄存器的选择装置。该数据寄存器电路是通过将多个寄存器排列在一条线上而形成的。利用这种结构，与常规器件相比，可以减少构成数据寄存器电路的寄存器的数量。因此，可以将寄存器布置在单行中，与传统器件相比，数据寄存器电路的面积可以急剧减小，有助于半导体存储器件的集成。

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