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1. 发明公开

EP1271334A3 High bandwidth storage device architecture 审中-公开
标题翻译：存储器体系结构具有高带宽
公开(公告)号：EP1271334A3
公开(公告)日：2003-05-28
申请号：EP02012321.2
申请日：2002-06-04
申请人： LSI LOGIC CORPORATION
发明人： Henry, Russel J. , Weber, Bret , Gates, Dennis E. , Sherman, John , Holt, Keith
IPC分类号： G06F13/40
CPC分类号： H04L12/2854 , G06F13/4022
摘要： The present invention is directed to high bandwidth storage device controller architecture. The present invention may utilize a fabric interconnect. This may enable features such as dynamic expansion of modules, use of external memory system, scalability of memory systems and scalability and/or connectivity of array controllers to create big storage complexes.

2. 发明授权

EP0756234B1 Method and apparatus for transferring data in a controller having a centralized memory 失效
标题翻译：一种用于在盘控制器与集中存储的数据传输的方法和装置
公开(公告)号：EP0756234B1
公开(公告)日：2001-11-14
申请号：EP96305396.2
申请日：1996-07-23
申请人： LSI Logic Corporation
发明人： Gates, Dennis E.
IPC分类号： G06F13/40 , G06F3/06
CPC分类号： G06F3/0601 , G06F13/4027 , G06F2003/0692

3. 发明公开

EP1074916A2 Hardware mechanism for managing cache structures in a data storage system 有权
标题翻译：五金 - Anordnung zur Verwaltung von Cachespeicherstrukturen in einem Datenspeichersystem
公开(公告)号：EP1074916A2
公开(公告)日：2001-02-07
申请号：EP00305591.0
申请日：2000-07-03
申请人： LSI LOGIC CORPORATION
发明人： DeKoning, Rodeny , Gates, Dennis E. , Kloeppner, John R.
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0871
摘要： A system and method for managing data stored in a cache block in a cache memory includes a cache block is located at a cache block address in the cache memory, and the data in the cache block corresponds to a storage location in a storage array identified by a storage location identifier. A storage processor accesses the cache block in the cache memory and provides a cache management command to a command processor. A processor memory coupled to the storage processor stores a search key based on the storage location identifier corresponding to the cache block. A command processor coupled to the storage processor receives a cache management command specified by the storage processor and transfers the storage location identifier from the processor memory. A cache management memory stores a cache management structure including the cache block address and the search key. A cache management processor is coupled to the cache management memory by a second link to manipulate the cache management structure in a hash table with linked lists at each hash queue element within the cache management memory in accordance with the cache management command and the search key.
摘要翻译：用于管理存储在高速缓存存储器中的高速缓存块中的数据的系统和方法包括高速缓存块位于高速缓冲存储器中的高速缓存块地址处，并且高速缓存块中的数据对应于存储阵列中的存储位置，存储位置标识符。存储处理器访问高速缓冲存储器中的高速缓存块，并向命令处理器提供高速缓存管理命令。耦合到存储处理器的处理器存储器基于与高速缓存块相对应的存储位置标识符存储搜索关键字。耦合到存储处理器的命令处理器接收由存储处理器指定的高速缓存管理命令，并从处理器存储器传送存储位置标识符。缓存管理存储器存储包括高速缓存块地址和搜索关键字的高速缓存管理结构。高速缓存管理处理器通过第二链路耦合到高速缓存管理存储器，以根据高速缓存管理命令和搜索关键来在高速缓存管理存储器内的每个散列队列元素处操作具有链表的哈希表中的高速缓存管理结构。

4. 发明公开

EP1074916A3 Hardware mechanism for managing cache structures in a data storage system 有权
标题翻译：用于管理数据存储系统中高速缓存的结构硬件结构
公开(公告)号：EP1074916A3
公开(公告)日：2004-06-30
申请号：EP00305591.0
申请日：2000-07-03
申请人： LSI Logic Corporation
发明人： DeKoning, Rodeny , Gates, Dennis E. , Kloeppner, John R.
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0871
摘要： A system and method for managing data stored in a cache block in a cache memory includes a cache block is located at a cache block address in the cache memory, and the data in the cache block corresponds to a storage location in a storage array identified by a storage location identifier. A storage processor accesses the cache block in the cache memory and provides a cache management command to a command processor. A processor memory coupled to the storage processor stores a search key based on the storage location identifier corresponding to the cache block. A command processor coupled to the storage processor receives a cache management command specified by the storage processor and transfers the storage location identifier from the processor memory. A cache management memory stores a cache management structure including the cache block address and the search key. A cache management processor is coupled to the cache management memory by a second link to manipulate the cache management structure in a hash table with linked lists at each hash queue element within the cache management memory in accordance with the cache management command and the search key.

5. 发明授权

EP1074916B1 Hardware mechanism for managing cache structures in a data storage system 有权
标题翻译：用于管理数据存储系统中高速缓存的结构硬件结构
公开(公告)号：EP1074916B1
公开(公告)日：2007-06-13
申请号：EP00305591.0
申请日：2000-07-03
申请人： LSI Logic Corporation
发明人： DeKoning, Rodeny , Gates, Dennis E. , Kloeppner, John R.
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0871

6. 发明公开

EP1271334A2 High bandwidth storage device architecture 审中-公开
标题翻译：高带宽存储设备架构
公开(公告)号：EP1271334A2
公开(公告)日：2003-01-02
申请号：EP02012321.2
申请日：2002-06-04
申请人： LSI LOGIC CORPORATION
发明人： Henry, Russel J. , Weber, Bret , Gates, Dennis E. , Sherman, John , Holt, Keith
IPC分类号： G06F13/40
CPC分类号： H04L12/2854 , G06F13/4022
摘要： The present invention is directed to high bandwidth storage device controller architecture. The present invention may utilize a fabric interconnect. This may enable features such as dynamic expansion of modules, use of external memory system, scalability of memory systems and scalability and/or connectivity of array controllers to create big storage complexes.
摘要翻译：本发明针对高带宽存储设备控制器架构。本发明可以利用织物互连。这可以实现诸如模块的动态扩展，使用外部存储器系统，存储器系统的可扩展性和可扩展性和/或阵列控制器的连接性以创建大型存储复合体等特征。

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