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1. 发明公开

EP0196084A3 Sequential logic circuit 失效
标题翻译：顺序逻辑电路
公开(公告)号：EP0196084A3
公开(公告)日：1988-06-15
申请号：EP86104150
申请日：1986-03-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shimizu, Hiroshi , Kaizuka, Masao
IPC分类号： H03K19/173
CPC分类号： H03K19/1733
摘要： @ A sequential logic circuit has a logic memory (2'), a preceding logic circuit (1'), a succeeding logic circuit (3'), and a function defining circuit (10). An input signal (4) is taken by the preceding logic circuit (1 '), where a new logic state (6) is produced based on the input signal (4) and a present logic state (5) in the logic memory (2') executing a defined calculation. The content of the logic memory (2') is taken over by the new logic state (6). The succeeding logic circuit (3') produces an output signal (7) based on the logic state (5) of the logic memory (2') executing a defined calculation. The calculation executed in the succeeding (1') or preceding (3') logic circuit is defined by the defining function circuit (10). Thus, the whole circuit operates with a desired function.

2. 发明公开

EP0196084A2 Sequential logic circuit 失效
标题翻译： Sequentielle logische Schaltung。
公开(公告)号：EP0196084A2
公开(公告)日：1986-10-01
申请号：EP86104150.7
申请日：1986-03-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shimizu, Hiroshi , Kaizuka, Masao
IPC分类号： H03K19/173
CPC分类号： H03K19/1733
摘要： @ A sequential logic circuit has a logic memory (2'), a preceding logic circuit (1'), a succeeding logic circuit (3'), and a function defining circuit (10). An input signal (4) is taken by the preceding logic circuit (1 '), where a new logic state (6) is produced based on the input signal (4) and a present logic state (5) in the logic memory (2') executing a defined calculation. The content of the logic memory (2') is taken over by the new logic state (6). The succeeding logic circuit (3') produces an output signal (7) based on the logic state (5) of the logic memory (2') executing a defined calculation. The calculation executed in the succeeding (1') or preceding (3') logic circuit is defined by the defining function circuit (10). Thus, the whole circuit operates with a desired function.
摘要翻译：顺序逻辑电路具有逻辑存储器（2分钟），前一逻辑电路（1分钟），后续逻辑电路（3分钟）和功能定义电路（10）。输入信号（4）由前一逻辑电路（1分钟）取得，其中基于输入信号（4）产生新的逻辑状态（6），并且逻辑存储器（2）中的当前逻辑状态（5） min）执行定义的计算。逻辑存储器的内容（2分钟）由新的逻辑状态（6）接管。后续逻辑电路（3分钟）基于执行定义的计算的逻辑存储器（2分钟）的逻辑状态（5）产生输出信号（7）。在后续（1分钟）或之前（3分钟）逻辑电路中执行的计算由定义功能电路（10）定义。因此，整个电路以期望的功能运行。

3. 发明授权

EP0196084B1 Sequential logic circuit 失效
标题翻译：顺序逻辑电路
公开(公告)号：EP0196084B1
公开(公告)日：1993-06-16
申请号：EP86104150.7
申请日：1986-03-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shimizu, Hiroshi , Kaizuka, Masao
IPC分类号： H03K19/173
CPC分类号： H03K19/1733

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