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1. 发明公开

EP3637246A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 有权
公开(公告)号：EP3637246A1
公开(公告)日：2020-04-15
申请号：EP19214143.0
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Shpeisman, Tatiana , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev , Galoppo Von Borries, Nicolas C.
IPC分类号： G06F7/483 , G06F7/544 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

2. 发明公开

EP2887218A8 UNBOUNDED TRANSACTIONAL MEMORY WITH FORWARD PROGRESS GUARANTEES USING A HARDWARE GLOBAL LOCK 审中-公开
标题翻译：使用全球五金锁具无限交易存储与转发进度保证
公开(公告)号：EP2887218A8
公开(公告)日：2016-02-17
申请号：EP14191779.9
申请日：2014-11-04
申请人： Intel Corporation
发明人： Gottschlich Justin E. , Calciu, Irina , Shpeisman, Tatiana , Pokam, Gilles A.
IPC分类号： G06F9/46 , G06F9/38 , G06F9/52 , G06F9/30
CPC分类号： G06F9/467 , G06F9/52 , G06F9/528
摘要： A processing device implementing unbounded transactional memory with forward progress guarantees using a hardware global lock is disclosed. A processing device of the disclosure includes a hardware transactional memory (HTM) hardware contention manager to cause a bounded transaction to be translated to an unbounded transaction, the unbounded transaction to acquire a global hardware lock for the unbounded transaction, the global hardware lock read by bounded transactions that abort when the global hardware lock is taken. The processing device further includes an execution unit communicably coupled to the HTM hardware contention manager to execute instructions of the unbounded transaction without speculation, the unbounded transaction to release the global hardware lock upon completion of execution of the instructions.

3. 发明公开

EP3937004A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 有权转让
公开(公告)号：EP3937004A1
公开(公告)日：2022-01-12
申请号：EP21195277.5
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Galoppo von Borries, Nicolas C. , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev , Shpeisman, Tatiana
IPC分类号： G06F7/483 , G06F7/544 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： The present disclosure provides a graphics processing unit, GPU, comprising: a plurality of memory controllers, a cache memory coupled with the plurality of memory controllers, a a graphics multiprocessor coupled with the cache memory and the plurality of memory controllers. The graphics multiprocessor having a single instruction, multiple thread, SIMT, architecture. The graphics multiprocessor includes a register file and a plurality of compute units coupled with the register file. The plurality of compute units including a first compute unit to perform a mixed precision matrix operation and a second compute unit to perform, in response to a single instruction, multiple compute operations, wherein the multiple compute operations include a fused multiply-add operation and a rectified linear unit operation applied to an output of the fused multiply-add operation.

4. 发明公开

EP4290370A1 GENERAL PURPOSE GRAPHICS COMPUTE UNIT AND METHOD TO EXECUTE INSTRUCTIONS OF MIXED PRECISION 审中-实审
公开(公告)号：EP4290370A1
公开(公告)日：2023-12-13
申请号：EP23181292.6
申请日：2018-03-14
申请人： Intel Corporation
发明人： Ould-Ahmed-Vall, ElMoustapha , Lakshmanan, Barath , Shpeisman, Tatiana , Ray, Joydeep , Tang, Ping T. , Strickland, Michael , Chen, Xiaoming , Yao, Anbang , Ashbaugh, Ben J. , Hurd, Linda L. , Ma, Liwei
IPC分类号： G06F9/30 , G06F9/38 , G06T15/00
摘要： One embodiment provides for data processing system to perform machine learning operations. The data processing system comprises: a memory device configured to store instructions; a graphics processing unit (GPU) to execute the instructions. The instructions include a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, and the second instruction to cause the GPU to perform an integer operation. A general-purpose graphics compute unit included within the GPU has a single instruction, multiple thread architecture and is to execute the first instruction concurrently with execution of the second instruction.

5. 发明公开

EP4130976A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 审中-公开
公开(公告)号：EP4130976A1
公开(公告)日：2023-02-08
申请号：EP22198967.6
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Galoppo von Borries, Nicolas , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev , Shpeisman, Tatiana
IPC分类号： G06F7/544 , G06F7/483 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： The present disclosure provides a method, a data processing system and a graphics processing unit, GPU, comprising a memory controller; and a graphics multiprocessor coupled with the memory controller. The graphics multiprocessor includes a plurality of compute units configured to execute an instruction to perform a mixed-precision matrix operation on first input data and second input data; generate intermediate data based on a result of the mixed-precision matrix operation; convert the intermediate data to a floating-point format determined based on statistics associated with first output data; and output, as second output data, the converted intermediate data in the determined floating-point format.

6. 发明公开

EP3859519A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 有权
公开(公告)号：EP3859519A1
公开(公告)日：2021-08-04
申请号：EP21165109.6
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Shpeisman, Tatiana , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Galoppo von Borries, Nicolas C. , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev
IPC分类号： G06F7/483 , G06F7/544 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： The present disclosure provides an apparatus comprising a memory interface, an array of processing clusters each including a multiprocessor unit coupled to the memory interface, wherein at least one multiprocessor unit is to execute a fused multiply-add instruction in parallel across multiple threads. The at least one multiprocessor unit comprising a register file to store data, and a compute unit coupled to the register file, wherein the compute unit is to execute a fused multiply-add instruction on matrix data. The compute unit comprising hardware logic to quantize the data from a higher precision, including a 32-bit floating point format to a lower precision floating point format, including a 16-bit floating point format, having a 1-bit sign, an 8-bit exponent, and a mantissa, wherein fewer bits are used for the mantissa of the lower precision floating point format; and one or more logic units to perform the fused multiply-add operation on the data in the lower precision floating point format.

7. 发明公开

EP3796154A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 审中-公开
公开(公告)号：EP3796154A1
公开(公告)日：2021-03-24
申请号：EP20207059.5
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Shpeisman, Tatiana , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Galoppo von Borries, Nicolas C. , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev
IPC分类号： G06F7/544 , G06F7/483 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： One embodiment provides for an apparatus comprising: an interconnect fabric; a memory interface coupled to the interconnect fabric; an input/output, IO, unit coupled to the interconnect fabric; an array of multiprocessors coupled to the interconnect fabric, a multiprocessor in the array of multiprocessors to execute a mixed-precision instruction in parallel across multiple threads. The multiprocessor in the array of multiprocessors comprises: a plurality of registers to store packed floating-point operand values; and execution circuitry to execute one or more of the mixed-precision instructions to perform a fused multiply-accumulate operation. The execution circuitry comprises: a 16-bit multiplier to multiply a first 16-bit floating point source value and a second 16-bit floating point source value to generate an intermediate result; and a 32-bit accumulator to add the intermediate result to an accumulated floating-point value to generate a new accumulation result.

8. 发明公开

EP3657323A1 COMPUTE OPTIMIZATION MECHANISM 有权
公开(公告)号：EP3657323A1
公开(公告)日：2020-05-27
申请号：EP19218464.6
申请日：2018-03-02
申请人： Intel Corporation
发明人： Appu, Abhishek R. , Koker, Altug , Hurd, Linda L. , Kim, Dukhwan , MacPherson, Mike B. , Weast, John C. , Chen, Feng , Akhbari, Farshad , Srinivasa, Narayan , Satish, Nadathur Rajagopalan , Tang, Ping T. , Ray, Joydeep , Strickland, Michael S. , Chen, Xiaoming , Yao, Anbang , Shpeisman, Tatiana
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06T1/20 , G06N3/063 , G06F3/14 , G06N3/04 , G06N3/08 , G06T15/00 , G09G5/36
摘要： A graphics processing unit has a set of memory controllers, a cache memory, and at least one compute cluster with at least one graphics multiprocessor coupled to the set of memory controllers. The at least one graphics multiprocessor includes an instruction unit, a plurality of processing cores, and a shared memory coupled to the plurality of processing cores. The instruction unit is configured to dispatch instructions for execution by a processing core. Execution of a mixed precision fused multiply-accumulate, FMAC, operation is supported by a compute mechanism, wherein the FMAC operation comprises an arithmetic logic unit, ALU, operation of D = A ∗ B + C with A and B being 8-bit integer data elements, and C being a 32-bit integer data element.

9. 发明公开

EP3637247A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 有权
公开(公告)号：EP3637247A1
公开(公告)日：2020-04-15
申请号：EP19214829.4
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Shpeisman, Tatiana , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev , Galoppo von Borries, Nicolas
IPC分类号： G06F7/483 , G06F7/544 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

10. 发明公开

EP2075690A1 Mechanism for strong atomicity in a transactional memory system 有权
标题翻译：机制解释系统
公开(公告)号：EP2075690A1
公开(公告)日：2009-07-01
申请号：EP08254178.0
申请日：2008-12-30
申请人： Intel Corporation
发明人： Saha, Bratin , Adl-Tabatabai, Ali-Reza , Wang, Cheng , Shpeisman, Tatiana
IPC分类号： G06F9/312 , G06F9/38 , G06F9/46
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/467
摘要： A method and apparatus for providing efficient strong atomicity is herein described. Optimized strong atomic operations may be inserted at non-transactional read accesses to provide efficient strong atomicity. A global transaction value is copied at a beginning of a non-transactional function to a local transaction value; essentially creating a local timestamp of the global transaction value. At a non-transactional memory access within the function, a counter value or version value is compared to the LTV to see if a transaction has started updating memory locations, or specifically the memory location accessed. If memory locations have not been updated by a transaction, execution is accelerated by avoiding a full set of slowpath strong atomic operations to ensure validity of data accessed. In contrast, the slowpath operations may be executed to resolve contention between a transactional and non-transaction access contending for the same memory location.
摘要翻译：这里描述了提供有效的强原子性的方法和装置。可以在非事务读访问中插入优化的强原子操作，以提供有效的强原子性。全局事务值在非事务函数的开始被复制到本地事务值; 基本上创建了全局事务值的本地时间戳。在功能内的非事务性存储器访问中，将计数器值或版本值与LTV进行比较，以查看事务是否已开始更新存储器位置，或具体地访问存储器位置。如果事务没有更新存储器位置，则可以通过避免一整套慢路强原子操作来加速执行，以确保访问的数据的有效性。相比之下，可以执行慢路操作来解决争用相同内存位置的事务和非事务访问之间的争用。

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