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1. 发明公开

EP1055998A2 Reducing the number of issued instructions in a microprocessor 有权
标题翻译：威廉·德·安扎尔·冯·奥斯基本·贝弗伦
公开(公告)号：EP1055998A2
公开(公告)日：2000-11-29
申请号：EP00108310.4
申请日：2000-04-15
申请人： Infineon Technologies North America Corp.
发明人： Singh, Balraj , Mattela, Venkat , Chesters, Eric , Fleck, Rod G.
IPC分类号： G06F9/38
CPC分类号： G06F9/381
摘要： A method and an apparatus for reducing the number of instruction transactions in a microprocessor are disclosed. As a method, the number of issued instructions carried by an issued instruction bus in a computer system are reduced by determining if an instruction fetched by a fetch unit matches a cached instruction tag. When the fetched instruction matches the cached instruction tag, an opcode and an associated instruction corresponding to the cached instruction tag are directly injected to an appropriate function unit. The apparatus includes a plurality of tag PC cache memory devices used to store tag PC entries associated with target instructions injected directly to corresponding function units included microprocessors and the like. The injection reduces the number of instructions fetched from the program memory as well as the number of issued instructions carried by an issued instruction bus.
摘要翻译：公开了一种用于减少微处理器中的指令事务数量的方法和装置。作为一种方法，通过确定由获取单元获取的指令是否匹配缓存的指令标签来减少由计算机系统中发出的指令总线承载的发出指令的数量。当获取的指令与高速缓存的指令标签匹配时，与缓存的指令标签相对应的操作码和关联指令被直接注入到适当的功能单元中。该装置包括多个标签PC缓存存储器件，用于存储与直接注入到包括微处理器等的功能单元的目标指令相关联的标签PC条目。注入减少了从程序存储器提取的指令数量以及发出的指令总线所携带的已发出指令的数量。

2. 发明授权

EP1455271B1 DATA PROCESSOR WITH PARALLEL DECODING AND EXECUTION OF DATA AND ADDRESS INSTRUCTIONS 有权
标题翻译：用数据和地址的命令的并行解码和执行的数据处理
公开(公告)号：EP1455271B1
公开(公告)日：2011-10-26
申请号：EP03029612.3
申请日：1998-09-04
申请人： Infineon Technologies North America Corp.
发明人： Fleck, Rod G. , Baror, Gigy , Moeller, Ole H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3891 , G06F9/3013 , G06F9/30141 , G06F9/381 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3889

3. 发明公开

EP1406165A3 Decoupled architecture processor with loop pipeline 有权
标题翻译：解耦处理器架构与循环管道
公开(公告)号：EP1406165A3
公开(公告)日：2004-12-01
申请号：EP03029611.5
申请日：1998-09-04
申请人： Infineon Technologies North America Corp.
发明人： Fleck, Rod G. , Baror, Gigy , Moeller, Ole H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3891 , G06F9/3013 , G06F9/30141 , G06F9/381 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3889
摘要： The present invention relates to a data processor which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a third pipeline for executing loop instructions, a unit for issuing multiple instructions to said pipelines, a first set of registers being coupled with said first pipeline, and a second set of registers being coupled with said second pipeline and said third pipeline, wherein first second and third pipelines process data in parallel.

4. 发明公开

EP1455271A3 DATA PROCESSOR WITH PARALLEL DECODING AND EXECUTION OF DATA AND ADDRESS INSTRUCTIONS 审中-公开
标题翻译：具有并行解码和执行数据和地址指令的数据处理器
公开(公告)号：EP1455271A3
公开(公告)日：2005-08-31
申请号：EP03029612.3
申请日：1998-09-04
申请人： Infineon Technologies North America Corp.
发明人： Fleck, Rod G. , Baror, Gigy , Moeller, Ole H.
IPC分类号： G06F9/38
摘要： The present invention relates to a data processor which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to said pipelines, a first set of registers being coupled with said first pipeline, and a second set of registers being coupled with said second pipeline, wherein first and second pipeline process data in parallel.
摘要翻译：本发明涉及一种数据处理器，它包括用于解码和执行数据指令的第一流水线，用于解码和执行地址指令的第二流水线，用于向所述流水线发出多个指令的单元，第一组寄存器与所述第一流水线，并且第二组寄存器与所述第二流水线耦合，其中第一和第二流水线并行处理数据。

5. 发明公开

EP1406165A2 Decoupled architecture processor with loop pipeline 有权
标题翻译： Entkoppelte Prozessorarchitektur mit Schleifen-Pipeline
公开(公告)号：EP1406165A2
公开(公告)日：2004-04-07
申请号：EP03029611.5
申请日：1998-09-04
申请人： Infineon Technologies North America Corp.
发明人： Fleck, Rod G. , Baror, Gigy , Moeller, Ole H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3891 , G06F9/3013 , G06F9/30141 , G06F9/381 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3889
摘要： The present invention relates to a data processor which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions a third pipeline for executing loop instructions, a unit for issuing multiple instructions to said pipelines, a first set of registers being coupled with said first pipeline, and a second set of registers being coupled with said second pipeline and said third pipeline, wherein first second and third pipelines process data in parallel.
摘要翻译：有两条管道，一条用于数据指令，另一条用于地址指令。一个单元向管道发出多个指令。两组寄存器分别连接到管道。管道并行处理数据。

6. 发明公开

EP1055998A3 Reducing the number of issued instructions in a microprocessor 有权
标题翻译：减少微处理器发出的指令数
公开(公告)号：EP1055998A3
公开(公告)日：2001-01-31
申请号：EP00108310.4
申请日：2000-04-15
申请人： Infineon Technologies North America Corp.
发明人： Singh, Balraj , Mattela, Venkat , Chesters, Eric , Fleck, Rod G.
IPC分类号： G06F9/38
CPC分类号： G06F9/381
摘要： A method and an apparatus for reducing the number of instruction transactions in a microprocessor are disclosed. As a method, the number of issued instructions carried by an issued instruction bus in a computer system are reduced by determining if an instruction fetched by a fetch unit matches a cached instruction tag. When the fetched instruction matches the cached instruction tag, an opcode and an associated instruction corresponding to the cached instruction tag are directly injected to an appropriate function unit. The apparatus includes a plurality of tag PC cache memory devices used to store tag PC entries associated with target instructions injected directly to corresponding function units included microprocessors and the like. The injection reduces the number of instructions fetched from the program memory as well as the number of issued instructions carried by an issued instruction bus.

7. 发明公开

EP1455271A2 Data processor with parallel decoding and execution of data and address instructions 有权
标题翻译：用数据和地址的命令的并行解码和执行的数据处理
公开(公告)号：EP1455271A2
公开(公告)日：2004-09-08
申请号：EP03029612.3
申请日：1998-09-04
申请人： Infineon Technologies North America Corp.
发明人： Fleck, Rod G. , Baror, Gigy , Moeller, Ole H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3891 , G06F9/3013 , G06F9/30141 , G06F9/381 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3889
摘要： The present invention relates to a data processor which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to said pipelines, a first set of registers being coupled with said first pipeline, and a second set of registers being coupled with said second pipeline, wherein first and second pipeline process data in parallel.
摘要翻译：本发明涉及一种数据处理器，其包括用于用于发出多个指令至所述管道的解码和执行数据的指令，用于解码的第二管道和执行地址的说明，一个单元的第一管道，第一组寄存器被耦合到所述第一管道，以及第二组寄存器耦合与所述第二管道，平行worin第一和第二流水线处理数据。

8. 发明授权

EP0902367B1 Data processing unit with debug capabilities 有权
标题翻译：具有调试功能的数据处理单元
公开(公告)号：EP0902367B1
公开(公告)日：2003-05-28
申请号：EP98117015.2
申请日：1998-09-09
申请人： Infineon Technologies North America Corp.
发明人： Chesters, Eric , Arnold, Roger D. , Fleck, Rod G.
IPC分类号： G06F11/36
CPC分类号： G06F11/3636 , G06F11/3656

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