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1. 发明公开

EP3234766A4 LIGHTWEIGHT RESTRICTED TRANSACTIONAL MEMORY FOR SPECULATIVE COMPILER OPTIMIZATION 审中-公开
公开(公告)号：EP3234766A4
公开(公告)日：2018-07-04
申请号：EP15870562
申请日：2015-11-16
申请人： INTEL CORP
发明人： WANG CHENG , WU YOUFENG , BAGHSORKHI SARA S , HARTONO ALBERT , VALENTINE ROBERT
IPC分类号： G06F9/30 , G06F8/41 , G06F9/38 , G06F12/08
CPC分类号： G06F9/528 , G06F8/41 , G06F8/4451 , G06F9/3004 , G06F9/30087 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F12/0828 , G06F12/0875 , G06F2212/452
摘要： Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

2. 发明公开

EP2972796A4 METHODS AND APPARATUS TO MANAGE CONCURRENT PREDICATE EXPRESSIONS 审中-公开
标题翻译： VERFAHREN UND VORRICHTUNGFÜRDIE VERWALTUNG SIMULANERPRÄDIKATIVERAUSDRÜCKE
公开(公告)号：EP2972796A4
公开(公告)日：2016-10-26
申请号：EP14763196
申请日：2014-01-14
申请人： INTEL CORP
发明人： GOTTSCHLICH JUSTIN E , PEREIRA CRISTIANO LIGIERI , POKAM GILLES , WU YOUFENG
IPC分类号： G06F9/38 , G06F9/46 , G06F11/36
CPC分类号： G06F9/52 , G06F11/3632
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.
摘要翻译：公开了方法，装置，系统和制品以管理并发谓词表达。一个示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行直到满足第一条件，并且当满足第二条件时识别并发冲突。

3. 发明公开

EP3198403A4 PERSISTENT STORE FENCE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
公开(公告)号：EP3198403A4
公开(公告)日：2018-05-30
申请号：EP15845271
申请日：2015-08-31
申请人： INTEL CORP
发明人： WANG CHENG , WU YOUFENG , SANKARAN RAJESH M
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/30145 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3855 , G06F9/3859 , G06F9/466 , G06F12/0804 , G06F12/0815 , G06F12/0875 , G06F2212/452
摘要： A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed.

4. 发明公开

EP3060984A4 CONJUGATE CODE GENERATION FOR EFFICIENT DYNAMIC OPTIMIZATIONS 审中-公开
标题翻译： KONJUGATCODEERZEUGUNGFÜREFFIZIENTE DYNAMISCHE OPTIMIERUNGEN
公开(公告)号：EP3060984A4
公开(公告)日：2017-05-31
申请号：EP13895899
申请日：2013-10-24
申请人： INTEL CORP
发明人： RONG HONGBO , PARK HYUNCHUL , WANG CHENG , WU YOUFENG
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/4552 , G06F8/4442 , G06F8/52 , G06F9/45508 , G06F9/45533

5. 发明公开

EP2875427A4 ALLOCATION OF ALIAS REGISTERS IN A PIPELINED SCHEDULE 有权
标题翻译：伊朗伊朗伊斯兰共和国的黎巴嫩民族解放阵线
公开(公告)号：EP2875427A4
公开(公告)日：2016-07-13
申请号：EP13885974
申请日：2013-05-30
申请人： INTEL CORP
发明人： RONG HONGBO , WANG CHENG , PARK HYUNCHUL , WU YOUFENG
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38 , G06F13/16
CPC分类号： G06F9/3838 , G06F8/434 , G06F8/441 , G06F8/443 , G06F9/30127 , G06F9/3017 , G06F9/3834 , G06F9/384
摘要： In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。存储器范围信息引用存储器内的一个或多个存储器位置。该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的相应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作循环和循环的后续迭代中的第二操作。该系统还包括耦合到处理器的存储器。描述和要求保护其他实施例。

6. 发明公开

EP2901266A4 FLEXIBLE ACCELERATION OF CODE EXECUTION 有权
标题翻译：灵活的BESCHLEUNIGUNG EINERCODEAUSFÜHRUNG
公开(公告)号：EP2901266A4
公开(公告)日：2016-05-25
申请号：EP13841895
申请日：2013-09-26
申请人： INTEL CORP
发明人： WANG CHENG , WU YOUFENG
IPC分类号： G06F9/06 , G06F9/30 , G06F9/455
CPC分类号： G06F9/4552 , G06F8/44 , G06F9/45516 , G06F9/45533 , G06F9/45554 , Y02D10/26 , Y02D10/28
摘要： Technologies for performing flexible code acceleration on a computing device includes initializing an accelerator virtual device on the computing device. The computing device allocates memory-mapped input and output (I/O) for the accelerator virtual device and also allocates an accelerator virtual device context for a code to be accelerated. The computing device accesses a bytecode of the code to be accelerated and determines whether the bytecode is an operating system-dependent bytecode. If not, the computing device performs hardware acceleration of the bytecode via the memory-mapped I/O using an internal binary translation module. However, if the bytecode is operating system-dependent, the computing device performs software acceleration of the bytecode.
摘要翻译：在计算设备上执行灵活代码加速的技术包括在计算设备上初始化加速器虚拟设备。计算设备为加速器虚拟设备分配内存映射输入和输出（I / O），并为加速的代码分配加速器虚拟设备上下文。计算设备访问要加速的代码的字节码，并确定字节码是否是依赖于操作系统的字节码。如果不是，则计算设备通过使用内部二进制翻译模块的内存映射I / O执行字节码的硬件加速。但是，如果字节码与操作系统有关，则计算设备执行字节码的软件加速。

7. 发明公开

EP2588958A4 APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE 有权
标题翻译：设备，方法和系统的能效功率耦合第一核型与第二次核TYPE INCREASE
公开(公告)号：EP2588958A4
公开(公告)日：2016-11-02
申请号：EP11804047
申请日：2011-06-22
申请人： INTEL CORP
发明人： WU YOUFENG , HU SHILIANG , BORIN EDSON , WANG CHENG C , BRETERNITZ MAURICIO JR , LIU WEI
IPC分类号： G06F9/46 , G06F1/32 , G06F9/30 , G06F9/38 , G06F9/48
CPC分类号： G06F9/30076 , G06F9/30174 , G06F9/3879 , G06F9/4893 , Y02D10/24
摘要： An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

8. 发明公开

EP2956853A4 SOFTWARE PIPELINING AT RUNTIME 审中-公开
标题翻译：软件管道WÄHRENDDER LAUFZEIT
公开(公告)号：EP2956853A4
公开(公告)日：2016-10-19
申请号：EP14775994
申请日：2014-03-27
申请人： INTEL CORP
发明人： RONG HONGBO , PARK HYUNCHUL , WU YOUFENG
IPC分类号： G06F9/38 , G06F9/45 , G06F9/46
CPC分类号： G06F8/4452 , G06F8/433

9. 发明公开

EP2901289A4 METHODS, SYSTEMS AND APPARATUS TO CACHE CODE IN NON-VOLATILE MEMORY 审中-公开
标题翻译：方法，系统和设备代码，缓存在非易失性存储器
公开(公告)号：EP2901289A4
公开(公告)日：2016-04-13
申请号：EP13840642
申请日：2013-09-19
申请人： INTEL CORP
发明人： CHUNG JAEWOONG , WU YOUFENG , WANG CHENG
IPC分类号： G06F12/08 , G06F9/00 , G06F9/45 , G06F9/455 , G06F12/02
CPC分类号： G06F12/0888 , G06F9/4552 , G06F12/0246 , G06F12/0897 , G06F2212/452
摘要： Methods and apparatus are disclosed to cache code in non-volatile memory. A disclosed example method includes identifying an instance of a code request for first code, identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache, and when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.
摘要翻译：的方法和设备是光盘的非易失性存储器，以游离缺失高速缓存的代码。一种盘游离缺失实施例的方法包括在用于第一码的代码请求的实例标识，标识是否所述第一代码存储在非易失性（NV）的随机存取存储器（RAM）高速缓存，并且当所述第一代码是从所述NV RAM缓存不存在，将所述第一代码到NV RAM缓存当与第一代码相关联的第一条件被满足，并且当第一条件不被满足防止第一代码到NV RAM缓存的存储。

10. 发明公开

EP2761478A4 BI-DIRECTIONAL COPYING OF REGISTER CONTENT INTO SHADOW REGISTERS 审中-公开
标题翻译： TAB含量的影子寄存器双向COPY
公开(公告)号：EP2761478A4
公开(公告)日：2015-10-28
申请号：EP11873137
申请日：2011-09-29
申请人： INTEL CORP
发明人： WANG CHENG , WU YOUFENG , CHUNG JAEWOONG
IPC分类号： G06F13/14 , G06F9/30 , G06F12/00
CPC分类号： G06F3/065 , G06F9/30116 , G06F9/30123 , G06F9/3863

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