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1. 发明公开

EP1036414A4 CHIP SCALE PACKAGE USING LARGE DUCTILE SOLDER BALLS 有权
标题翻译： CSP-PACKUNG MIT GROSSEN DUKTIELENLÖTKUGELN
公开(公告)号：EP1036414A4
公开(公告)日：2001-11-14
申请号：EP98953717
申请日：1998-10-19
申请人： FLIP CHIP TECHNOLOGIES L L C
发明人： ELENIUS PETER , HOLLACK HARRY
IPC分类号： H01L23/52 , G06F1/16 , H01L21/3205 , H01L21/60 , H01L23/12 , H01L23/31 , H01L23/48 , H01L23/485 , H01L29/40
CPC分类号： H01L24/12 , G06F1/1601 , G06F2200/1612 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05647 , H01L2224/10 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01051 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A chip scale package design (8) for a flip chip integrated circuit (10) includes a redistribution metal layer upon the upper surface of a semiconductor wafer (14) for simultaneaously forming solder bump pads (26) as well as the metal redistribution traces (30) that electrically couple such solder bump pads with the condutive bond pads (18) of the underlying integrated circuit (10). A patterned passivation layer (32) is applied over the redistribution metal layer (30). Relatively large, ductile solder balls (28) are placed on the solder bump pads (26) for mounting the chip scale package (8) to a circuit board or other substrate without the need for an underfill material. The back side (16) of the semiconductor wafer can be protected by a coating (34) for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
摘要翻译：用于倒装芯片集成电路（10）的芯片级封装设计（8）包括在半导体晶片（14）的上表面上的再分布金属层，用于同时形成焊料凸块焊盘（26）以及金属再分布迹线 30），其将这种焊料凸块焊盘与下面的集成电路（10）的导电焊盘（18）电耦合。图案化的钝化层（32）被施加在再分布金属层（30）上。相对较大的可延展的焊球（28）被放置在焊料凸点焊盘（26）上，用于将芯片尺寸封装（8）安装到电路板或其他衬底而不需要底部填充材料。在处理期间，半导体晶片的背面（16）可以由用于机械强度的涂层（34）保护。还公开了在晶片处理级上形成这种芯片级封装的方法。

2. 发明公开

EP1664936A4 FORMING PARTIAL-DEPTH FEATURES IN POLYMER FILM 有权
标题翻译：结构元素 - 偏深的聚合物薄膜培训
公开(公告)号：EP1664936A4
公开(公告)日：2008-04-09
申请号：EP04809811
申请日：2004-09-27
申请人： FLIP CHIP TECHNOLOGIES L L C
发明人： JOHNSON MICHAEL E , ELENIUS PETER
IPC分类号： G03F1/14 , G03C5/00 , G03F20060101 , G03F9/00 , G21K5/00
CPC分类号： G03F1/50
摘要： A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101-2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature. The photomask may also have chrome of width greater than the critical dimension and spaced from other chrome by a distance greater than the critical dimension, which produces a full-depth feature through the entire thickness of the polymer film. The partial-depth feature and the full-depth feature are produced substantially simultaneously during a single series of photo-imaging steps. By preselecting a size, shape and distance between the chrome, the photomask is capable of inscribing discernable markings on the polymer layer, of changing the thickness of the polymer layer, and of changing an optical property of the surface of the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. § 1.72(b).

3. 发明公开

EP1665363A4 WAFER-LEVEL MOAT STRUCTURES 审中-公开
标题翻译： MOAT结构晶圆-LEVEL
公开(公告)号：EP1665363A4
公开(公告)日：2006-11-15
申请号：EP04785094
申请日：2004-09-27
申请人： FLIP CHIP TECHNOLOGIES L L C
发明人： JOHNSON MICHAEL E , ELENIUS PETER , KIM DEOK HOON
IPC分类号： H01L21/66 , H01L20060101 , H01L21/44 , H01L21/60 , H01L23/31 , H01L23/485
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05567 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).

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