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2. 发明公开

EP0405968A1 Clock recovery for serial data communications system 失效
标题翻译： Taktrückgewinnungfürein serielles Datenkommunikationssystem。
公开(公告)号：EP0405968A1
公开(公告)日：1991-01-02
申请号：EP90307072.0
申请日：1990-06-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Davies, David C. , Vonada, Donald G.
IPC分类号： H04L7/033 , H03L7/06
CPC分类号： H04L7/033
摘要： In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage-controlled oscillator (42) in response to the difference in phase between the incoming data signal (13) and the clock oscillator output (43). A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output (43). A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to seek an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal. The control circuitry includes a counter for counting transitions of the clock to inhibit another detect operation from starting until three transitions after one has begun.
摘要翻译：在串行数据通信系统中，通过响应于输入数据信号（13）和（13）之间的相位差而递增地控制压控振荡器（42）的频率（因此相位），从数据信号恢复嵌入时钟时钟振荡器输出（43）。检测数据信号的转换并用于启动在时钟振荡器输出（43）中的下一个转换时终止的控制脉冲。还产生一个参考脉冲，其宽度大约等于时钟的半周期。这些脉冲用于产生振荡器的电压控制，使得相位关系变化以寻求脉冲具有相等宽度的平衡，并且时钟的转变位于数据信号的电位转换的中点。该控制可以容忍相对较长的时间段，其中不存在数据信号的转变。控制电路包括用于对时钟的转变进行计数的计数器，以禁止另一个检测操作从一开始到一个开始之后的三个转换。

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