专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP2577395B1 PROCEDE DE LITHOGRAPHIE A DEDOUBLEMENT DE PAS 有权
公开(公告)号：EP2577395B1
公开(公告)日：2019-08-28
申请号：EP11721525.1
申请日：2011-05-25
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： PAIN, Laurent , BELLEDENT, Jérôme , BARNOLA, Sébastien
IPC分类号： G03F7/00 , H01L21/033 , H01L21/768 , H01L21/311 , B81C1/00

2. 发明授权

EP1695145B1 PROCÉDÉ DE RÉPARATION D' ERREURS DE MOTIFS RÉALISÉS DANS DES COUCHES MINCES 有权
标题翻译： PROCÉDÉDERÉPARATIOND'ERREURS DE MOTIFSRÉALISÉSDANS DES COUCHES MINES
公开(公告)号：EP1695145B1
公开(公告)日：2017-08-23
申请号：EP04816552.6
申请日：2004-12-15
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： PAIN, Laurent
IPC分类号： G03F1/68
CPC分类号： H01L21/32139 , B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/72 , H01L21/31144

3. 发明公开

EP2577395A1 PROCEDE DE LITHOGRAPHIE A DEDOUBLEMENT DE PAS 审中-公开
标题翻译： LITHOGRAFISCHES VERFAHRENFÜRDOPPELTEILUNG
公开(公告)号：EP2577395A1
公开(公告)日：2013-04-10
申请号：EP11721525.1
申请日：2011-05-25
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： PAIN, Laurent , BELLEDENT, Jérôme , BARNOLA, Sébastien
IPC分类号： G03F7/00 , B81C1/00
CPC分类号： B44C1/227 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F7/0035 , H01L21/0337 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L21/76897
摘要： The invention relates to lithography for etching very high-density patterns on a substrate, for example for producing microelectronic integrated circuits. A high-density pattern is etched using a combination of a plurality of less-dense partial patterns; a sacrificial film is formed on a substrate (10) and the sacrificial film is etched in a first partial pattern; spacers are formed on the edges of the elements of the sacrificial film thus etched, the spacers defining a second partial pattern; and then the sacrificial film is removed so as to leave in place only the spacers (16). Next, a film (22) sensitive to an electron beam is deposited between the spacers with a thickness that is smaller than or equal to the height of the spacers; and this sensitive film is exposed, by means of an electron beam, in a third partial pattern such that there remains on the substrate a final pattern of regions containing no spacers and no sensitive film, this pattern resulting from the combination of the second and third partial patterns and having a higher density than each of the partial patterns.
摘要翻译：基于几个较不密集的部分图案的组合来蚀刻基底上的非常致密的图案的平版印刷方法; 在衬底上形成牺牲层，并根据第一部分图案进行蚀刻; 间隔物形成在牺牲层的元件的边缘上，间隔物限定第二部分图案; 然后去除牺牲层，仅留下间隔物。随后将电子束敏感的层沉积在间隔物之间的厚度小于或等于间隔物的高度，并且该敏感层根据第三部分图案使用电子束曝光，使得保留在基底上缺少间隔物和敏感层的区域的最终图案，该图案由第二和第三部分图案的组合产生并且具有比每个部分图案更高的密度。

4. 发明授权

EP1507286B1 Procédé de formation d'un réseau d'interconnexions d'un circuit intégré et procédé de formation d'un transistor à grille entourante 有权
标题翻译：集成电路用栅极umschliessendem网络连接，并且晶体管的制造方法的制造方法
公开(公告)号：EP1507286B1
公开(公告)日：2015-12-09
申请号：EP04103813.4
申请日：2004-08-06
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： CORONEL, Philippe , LAPLANCHE, Yves , PAIN, Laurent
IPC分类号： H01L21/027 , H01L21/768 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/0277 , H01L21/7682 , H01L29/42384 , H01L29/42392 , H01L29/78654

5. 发明授权

EP2577723B1 PROCEDE DE LITHOGRAPHIE POUR LA REALISATION DE RESEAUX DE CONDUCTEURS RELIES PAR DES VIAS 有权
标题翻译：光刻工艺用于生产网络免受AFFILIATED孔梯子基础
公开(公告)号：EP2577723B1
公开(公告)日：2014-07-02
申请号：EP11724393.1
申请日：2011-05-25
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： BELLEDENT, Jérôme , PAIN, Laurent , BARNOLA, Sébastien
IPC分类号： H01L21/768 , H01L21/033
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/76811 , H01L21/76813 , H01L21/76897

6. 发明公开

EP2577723A1 PROCEDE DE LITHOGRAPHIE POUR LA REALISATION DE RESEAUX DE CONDUCTEURS RELIES PAR DES VIAS 有权
标题翻译：光刻工艺用于生产网络免受AFFILIATED孔梯子基础
公开(公告)号：EP2577723A1
公开(公告)日：2013-04-10
申请号：EP11724393.1
申请日：2011-05-25
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： BELLEDENT, Jérôme , PAIN, Laurent , BARNOLA, Sébastien
IPC分类号： H01L21/768 , H01L21/033
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/76811 , H01L21/76813 , H01L21/76897
摘要： The invention pertains to the field of lithography for making two networks of conductors connected by vias in microelectronic integrated circuits. The method includes, after forming a first network of conductors buried (102) under an insulation layer (108): depositing and etching a sacrificial layer on a substrate; forming spacers along all the edges of the members of the sacrificial layer thus etched and subsequently removing said layer; and etching a masking layer. The method further comprises carrying out two consecutive etchings of the insulation layer at two consecutive depths, one being the depth of the conductors of the second network and the other being an additional depth necessary at the target locations of the vias. One of the etchings is determined by the masking layer (110) and corresponds to the location of the conductors of the second network, while the other is determined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias. The sequence of the etchings is not essential. After completion of the two etchings, the regions etched in the insulation material of the substrate are filled with a conductive material (130) that simultaneously forms the conductors and the vias.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式