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1. 发明授权

EP2932534B1 PIXELATED IMAGER WITH MOTFT AND PROCESS 有权
标题翻译：具有MOTFT和PROCESS的像素化成像器
公开(公告)号：EP2932534B1
公开(公告)日：2017-08-30
申请号：EP13863613.9
申请日：2013-12-09
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang
IPC分类号： H01L31/036 , H01L27/146 , H01L27/12 , H01L31/0368 , H01L31/0376 , H01L31/20
CPC分类号： H01L31/20 , H01L27/1225 , H01L27/1463 , H01L27/14632 , H01L27/14663 , H01L27/14687 , H01L27/14692 , H01L31/0368 , H01L31/0376 , Y02E10/50
摘要： A method of fabricating a pixelated imager includes providing a substrate with bottom contact layer and sensing element blanket layers on the contact layer. The blanket layers are separated into an array of sensing elements by trenches isolating adjacent sensing elements. A sensing element electrode is formed adjacent each sensing element overlying a trench and defining a TFT. A layer of metal oxide semiconductor (MOS) material is formed on a dielectric layer overlying the electrodes and on an exposed upper surface of the blanket layers defining the sensing element adjacent each TFT. A layer of metal is deposited on each TFT and separated into source/drain electrodes on opposite sides of the sensing element electrode. The metal forming one of the S/D electrodes contacts the MOS material overlying the exposed surface of the semiconductor layer, whereby each sensing element in the array is electrically connected to the adjacent TFT by the MOS material.
摘要翻译：一种制造像素化成像器的方法包括在接触层上提供具有底部接触层和感测元件覆盖层的衬底。通过隔离相邻感测元件的沟槽将覆盖层分成感测元件阵列。感测元件电极形成在覆盖沟槽并限定TFT的每个感测元件附近。一层金属氧化物半导体（MOS）材料形成在覆盖电极的介电层上以及在限定与每个TFT相邻的感测元件的覆盖层的暴露的上表面上。在每个TFT上沉积金属层，并在感测元件电极的相对侧分成源极/漏极电极。形成S / D电极中的一个的金属接触覆盖半导体层的暴露表面的MOS材料，由此阵列中的每个感测元件通过MOS材料电连接到相邻的TFT。

2. 发明公开

EP2467884A1 AMOLED WITH CASCADED OLED STRUCTURES 审中-公开
标题翻译： AMOLED具有级联OLED结构
公开(公告)号：EP2467884A1
公开(公告)日：2012-06-27
申请号：EP10810340.9
申请日：2010-07-19
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang
IPC分类号： H01L51/50
CPC分类号： H01L27/3244 , H01L27/3204 , H01L27/3246
摘要： An active matrix organic light emitting display includes a plurality of pixels with each pixel including at least one organic light emitting diode circuit. Each diode circuit producing a predetermined amount of light Im in response to power W applied to the circuit and including n organic light emitting diodes cascaded in series so as to increase voltage dropped across the cascaded diodes by the factor of n, where n is an integer greater than one. Each diode of the n organic light emitting diodes produces approximately 1/n of the predetermined amount of light Im so as to reduce current flowing in the diodes by 1/n. The organic light emitting diode circuit of each pixel includes a thin film transistor current driver with the cascaded diodes connected in the source/drain circuit so the current driver provides the current flowing in the diodes.

3. 发明公开

EP3005420A2 STABLE HIGH MOBILITY MOTFT AND FABRICATION AT LOW TEMPERATURE 审中-公开
标题翻译：维多利亚大卫·霍尔·迈尔斯
公开(公告)号：EP3005420A2
公开(公告)日：2016-04-13
申请号：EP14801432.7
申请日：2014-05-07
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang , FOONG, Fatt , MUSOLF, Juergen
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66969 , H01L21/02063 , H01L21/02565 , H01L21/02631 , H01L21/76805 , H01L21/76814 , H01L21/76895 , H01L27/1225 , H01L29/247 , H01L29/42384 , H01L29/517 , H01L29/518 , H01L29/66742 , H01L29/78603 , H01L29/78606 , H01L29/78618 , H01L29/78693 , H01L29/78696 , H01L2021/775
摘要： A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and
in situ . The layer of amorphous metal oxide has a mobility above 40 cm
2 /Vs and a carrier concentration in a range of approximately 10
18 cm
-3 to approximately 5xl0
19 cm
-3 . Source/drain contacts are positioned on the protective layer and in electrical contact therewith.
摘要翻译：制造稳定的高迁移率无定形MOTFT的方法包括提供其上形成有栅极的基板和位于栅极上方的栅介质层的步骤。通过溅射将载流子传输结构沉积在栅极介电层上。载流子传输结构包括邻近栅极电介质的非晶高迁移率金属氧化物层，以及沉积在无氧和原位沉积的无定形高迁移率金属氧化物层上的相对惰性的材料保护层。无定形金属氧化物层的迁移率高于40cm 2 / Vs，载流子浓度在约1018cm-3至约5×1019cm-3的范围内。源极/漏极触点位于保护层上并与其接触。

4. 发明公开

EP2715786A1 METAL OXIDE TFT WITH IMPROVED SOURCE/DRAIN CONTACTS 审中-公开
标题翻译：金属氧化物薄膜晶体管，改善源/漏极接触
公开(公告)号：EP2715786A1
公开(公告)日：2014-04-09
申请号：EP12796733.9
申请日：2012-05-16
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang , FOONG, Fatt
IPC分类号： H01L21/36 , H01L21/44 , H01L21/465
CPC分类号： H01L29/7869 , H01L21/428 , H01L29/45 , H01L29/66969 , H01L29/78606
摘要： A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
摘要翻译：一种在金属氧化物半导体薄膜晶体管中形成欧姆源极/漏极接触的方法包括提供具有带隙的栅极，栅极电介质，高载流子浓度金属氧化物半导体有源层以及间隔开的薄膜晶体管薄膜晶体管配置。间隔开的源极/漏极金属触点在有源层中限定沟道区域。在沟道区域附近提供氧化环境，并且在氧化环境中加热栅极和沟道区域以降低沟道区域中的载流子浓度。可选地或附加地，每个源极/漏极接触件包括位于金属氧化物半导体活性层上的非常薄的低功函数金属层，并且具有高功函数金属的阻挡层位于低功函数金属上。

5. 发明公开

EP2666187A1 DRIVING METHOD FOR IMPROVING STABILITY IN MOTFTS 审中-公开
标题翻译： DRIVE法解MOTFTS稳定性INCREASE
公开(公告)号：EP2666187A1
公开(公告)日：2013-11-27
申请号：EP12749286.6
申请日：2012-01-27
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang
IPC分类号： H01L29/10
CPC分类号： G09G3/3225 , G09G2310/063 , G09G2320/0204
摘要： A method of driving a display device includes providing an array of pixels including rows and columns of pixels, each pixel including a switching/driving transistor circuit and at least one light emitting device. Each row of pixels has a scan line and each column of pixels has a data line. The method further includes defining a frame period during which each pixel in the array of pixels is addressed and dividing the frame period into a write subframe, a display subframe, and a rest subframe. A scan pulse is supplied to each scan line, a data signal to each data line and the light emitting devices are disabled during the write subframe. The light emitting devices are enabled during the display subframe and the switching/driving transistor circuits are disabled. A rest pulse is supplied to all scan lines and the light emitting devices are disabled during the rest subframe.

6. 发明公开

EP2932534A1 PIXELATED IMAGER WITH MOTFET AND PROCESS 有权
标题翻译： PIXELBILDGEBER MIT MOTFT UND VERFAHREN
公开(公告)号：EP2932534A1
公开(公告)日：2015-10-21
申请号：EP13863613.9
申请日：2013-12-09
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang
IPC分类号： H01L31/036
CPC分类号： H01L31/20 , H01L27/1225 , H01L27/1463 , H01L27/14632 , H01L27/14663 , H01L27/14687 , H01L27/14692 , H01L31/0368 , H01L31/0376 , Y02E10/50
摘要： A method of fabricating a pixelated imager includes providing a substrate with bottom contact layer and sensing element blanket layers on the contact layer. The blanket layers are separated into an array of sensing elements by trenches isolating adjacent sensing elements. A sensing element electrode is formed adjacent each sensing element overlying a trench and defining a TFT. A layer of metal oxide semiconductor material is formed on a dielectric layer overlying the electrodes and on an exposed upper surface of the blanket layers defining the sensing element adjacent each TFT. A layer of metal is deposited on each TFT and separated into source/drain electrodes on opposite sides of the electrode.The metal forming one of the electrodes contacts the MOS material overlying the exposed surf ace of the semiconductor layer, whereby each sensing element in the array is electrically connected to the adjacent TFT by the MOS material.
摘要翻译：制造像素化成像器的方法包括在接触层上提供底层接触层和感测元件覆盖层。橡皮布层通过隔离相邻感测元件的沟槽分离成感测元件的阵列。感测元件电极邻近覆盖沟槽的每个感测元件形成并且限定TFT。一层金属氧化物半导体（MOS）材料形成在覆盖电极的电介质层上，并且在覆盖层的暴露的上表面上形成与每个TFT相邻的感测元件。在每个TFT上沉积一层金属，并在传感元件电极的相对侧分离成源极/漏极。形成S / D电极之一的金属接触覆盖半导体层的暴露表面的MOS材料，由此阵列中的每个感测元件通过MOS材料电连接到相邻的TFT。

7. 发明公开

EP2856251A1 MASK LEVEL REDUCTION FOR MOFET 审中-公开
标题翻译： MASOF LEVEL REDUCTION FOR MOFET
公开(公告)号：EP2856251A1
公开(公告)日：2015-04-08
申请号：EP13797618.9
申请日：2013-05-28
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang , FOONG, Fatt , LEE, Liu-chung
IPC分类号： G02F1/1343
CPC分类号： G02F1/134363 , G02F1/13439 , G02F1/1368 , G02F2001/134372 , G02F2001/136231 , G02F2001/136236 , H01L27/1225 , H01L27/1288
摘要： A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.
摘要翻译：制造具有减少的掩模操作的TFT和IPS的方法包括衬底，栅极，栅极和周围衬底表面上的栅极电介质层以及栅极电介质上的半导体金属氧化物。沟道保护层覆盖栅极以在半导体金属氧化物中限定沟道区域。在沟道保护层和暴露的半导体金属氧化物的一部分上图案化S / D金属层以限定IPS区域。有机介电材料在S / D端子上和IPS区域的相对侧上被图案化。对S / D金属进行蚀刻以暴露限定第一IPS电极的半导体金属氧化物。钝化层覆盖第一电极并且在钝化层上图案化透明导电材料层以限定覆盖第一电极的第二IPS电极。

8. 发明公开

EP2324492A2 STABLE AMORPHOUS METAL OXIDE SEMICONDUCTOR 审中-公开
标题翻译：稳定的无定形金属氧化物半导体
公开(公告)号：EP2324492A2
公开(公告)日：2011-05-25
申请号：EP09812301.1
申请日：2009-09-04
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang
IPC分类号： H01L21/322 , H01L31/00
CPC分类号： H01L29/04 , H01L21/00 , H01L21/02554 , H01L21/02565 , H01L21/02592 , H01L21/16 , H01L21/28556 , H01L27/1214 , H01L27/1225 , H01L29/24 , H01L29/7869 , H01L29/78693 , H01L51/5012
摘要： A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

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