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1. 发明公开

EP0680632A1 POWER MANAGEMENT SYSTEM FOR COMPUTER DEVICE INTERCONNECTION BUS 失效
标题翻译：计算机设备互连总线电源管理系统
公开(公告)号：EP0680632A1
公开(公告)日：1995-11-08
申请号：EP94909469.0
申请日：1994-01-12
申请人： APPLE COMPUTER, INC.
发明人： OPRESCU, Florin , TEENER, Michael, D.
IPC分类号： G06F1 , G06F3
CPC分类号： G06F1/3203 , G06F1/325
摘要： The power management system tracks the total amount of power drawn from a bus by devices connected to the bus and to the bus itself, based on the individual operational status of each device. The power manager system also tracks the total amount of power supplied to the bus. From this information the power manager system determines whether a power surplus exists sufficient to allow an additional device to operate or to allow a currently operating device to draw more power. Power usage requests received from devices connected to the bus are granted or denied by the power management system based on the determination of available power. The power management system additionally is capable of sequencing the use of several devices to allow the devices to each operate while maintaining the total power draw within an acceptable range. The system provides for efficient use of a limited amount of power to allow operation of more devices than conventionally allowed with a bus. The system also can activate power supply devices which are off-line via soft-power-on commands to increase the total amount of power available. The system is advantageously implemented with any bus system having devices drawing power from the bus from power supplies providing limited power.
摘要翻译：电源管理系统根据每个设备的独立运行状态，跟踪连接到总线和总线本身的设备从总线汲取的总电量。电源管理器系统还跟踪供应给总线的总电量。根据这些信息，功率管理器系统确定是否存在足够的功率剩余以允许额外的设备操作或允许当前操作的设备汲取更多的功率。基于可用功率的确定，由电力管理系统授予或拒绝从连接到总线的设备接收的电力使用请求。此外，电源管理系统还能够对多个设备的使用进行排序，以使设备各自运行，同时将总功耗控制在可接受的范围内。该系统提供有限的功率的有效使用，以允许操作比传统上总线所允许的更多的设备。该系统还可以通过软启动命令来激活脱机的电源设备，以增加可用的总功率。该系统有利地通过任何总线系统来实现，该总线系统具有从提供有限功率的电源向总线提供功率的设备。

2. 发明公开

EP0679275A1 A COMMUNICATION NODE WITH A FIRST BUS CONFIGURATION FOR ARBITRATION AND A SECOND BUS CONFIGURATION FOR DATA TRANSFER 失效
标题翻译：与第一总线配置仲裁和第二总线配置数据传输的通信节点。
公开(公告)号：EP0679275A1
公开(公告)日：1995-11-02
申请号：EP94908608.0
申请日：1994-01-12
申请人： APPLE COMPUTER, INC.
发明人： OPRESCU, Florin , VAN BRUNT, Roger, W.
IPC分类号： G06F1 , G06F13 , H04L29
CPC分类号： G06F1/325 , G06F1/26 , G06F1/305 , G06F1/32 , G06F1/3253 , G06F13/36 , Y02D10/151
摘要： A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus configuration for arbitration like a single bus. Following arbitration, the interconnected nodes provide a second configuration for high speed unidirectional data transfer without the bandwidth limitations of a single bus. Each node includes an arbiter, a data bus, a plurality of ports, a first multiplexer to select either the arbiter or the data bus, and a second multiplexer to select either the arbiter or the data bus. The data bus includes a transmit bus and a receive bus that are coupled with a repeater circuit that can resynchronize the data. During arbitration, the multiplexers select the arbiter to provide the function of a single bus for all the nodes. During data transfer, the multiplexers are configured for transmission of data. Furthermore, a node can function as a repeater and resynchronizer even if it is not connected to a local host or if the local host is turned off or otherwise nonoperational.

3. 发明授权

EP0674788B1 METHOD AND APPARATUS FOR ARBITRATING ON AN ACYCLIC DIRECTED GRAPH 失效
标题翻译： VERFAHREN UND GERAT ZUR ARBITRIERUNG AUF EINEN ACYCLISCHEN GERICHTETEN GRAPH
公开(公告)号：EP0674788B1
公开(公告)日：2005-04-27
申请号：EP94905422.5
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： OPRESCU, Florin
IPC分类号： G06F15/16 , G06F13/36
CPC分类号： H04L12/40078 , G06F13/36 , G06F13/37 , G06F15/17343 , H04L12/40084 , H04L45/48
摘要： A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
摘要翻译：总线仲裁方案在系统中实现，其中系统总线上的节点的任意组合已被解析成非循环有向图。节点的分层排列有一个节点被指定为根，而所有其他节点已经与它们所链接的节点建立了父/子关系。每个节点可以具有建立具有预定的确认优先级方案的多个连接的子端口。公平总线访问仲裁以对应于预定端口优先级的顺序提供总线授权，允许所有节点在总线上转向。根节点可以总是确定其优先访问状态以获得总线访问，这对于容纳需要等时数据传送的根节点是有用的。或者，可以实现令牌通过仲裁方案，其中根据上述预定端口优先级方案，总线访问令牌围绕节点传递。在检测到必要的错误或添加或删除与现有节点的连接时，可以由任何节点触发抢占总线初始化。

4. 发明授权

EP0677191B1 METHOD AND APPARATUS FOR TRANSMITTING NRZ DATA SIGNALS ACROSS AN ISOLATION BARRIER DISPOSED IN AN INTERFACE BETWEEN ADJACENT DEVICES ON A BUS 失效
标题翻译：方法和设备NRZ数据传输信号通过一个接口垒之间绝缘NEIGHBORS设备上的总线
公开(公告)号：EP0677191B1
公开(公告)日：2003-03-26
申请号：EP94905427.4
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： VAN BRUNT, Roger , OPRESCU, Florin
IPC分类号： G06F13/40 , H04L25/49 , H03M5/18
CPC分类号： G06F13/4072 , H03M5/18 , H04L25/0266 , H04L25/4925
摘要： The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has as a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus accross the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a hight transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving as input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.

5. 发明授权

EP0674790B1 METHOD AND APPARATUS FOR TRANSFORMING AN ARBITRARY TOPOLOGY COLLECTION OF NODES INTO AN ACYCLIC DIRECTED GRAPH 失效
标题翻译： METHOD AND APPARATUS FOR CONVERSION结集合的任何拓扑的IN无环向图
公开(公告)号：EP0674790B1
公开(公告)日：2002-03-13
申请号：EP94905424.1
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： OPRESCU, Florin
IPC分类号： G06F15/16
CPC分类号： H04L12/40078 , G06F15/17343 , G06F15/17381
摘要： A system and method are described which take an arbitrarily assembled collection of nodes on a bus or network and imposes an optimized hierarchical tree structure where there is only one root node. Nodes having both parent and child nodes are considered branch nodes while nodes having only parent nodes are leaf nodes. Loops or cycles in the physical topology are resolved into a logical topology that is acyclic and directed. A signaling scheme is developed in which nodes, via on board communications hardware, signal all connected nodes and respond accordingly until hierarchical relationships are established. Cycles are resolved by intelligently breaking links to yield an acyclic graph. Direction is established by each node recognizing its parent/child status with respect to connected nodes until a single node is established as a root node.

6. 发明公开

EP0677191A1 METHOD AND APPARATUS FOR TRANSMITTING NRZ DATA SIGNALS ACROSS AN ISOLATION BARRIER DISPOSED IN AN INTERFACE BETWEEN ADJACENT DEVICES ON A BUS 失效
标题翻译：方法和设备NRZ数据传输信号了其之间的NEIGHBORS设备的接口上的总线屏障绝缘。
公开(公告)号：EP0677191A1
公开(公告)日：1995-10-18
申请号：EP94905427.0
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： VAN BRUNT, Roger , OPRESCU, Florin
IPC分类号： G06F13 , H03K19 , H03M5 , H04L25
CPC分类号： G06F13/4072 , H03M5/18 , H04L25/0266 , H04L25/4925
摘要： The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has as a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus accross the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a hight transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving as input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.

7. 发明公开

EP0674790A1 METHOD AND APPARATUS FOR TRANSFORMING AN ARBITRARY TOPOLOGY COLLECTION OF NODES INTO AN ACYCLIC DIRECTED GRAPH 失效
标题翻译：转换IN无环结集合的任何拓扑的方法和设备向图。
公开(公告)号：EP0674790A1
公开(公告)日：1995-10-04
申请号：EP94905424.0
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： OPRESCU, Florin
IPC分类号： G06F13 , G06F15 , H04L12
CPC分类号： H04L12/40078 , G06F15/17343 , G06F15/17381
摘要： A system and method are described which take an arbitrarily assembled collection of nodes on a bus or network and imposes an optimized hierarchical tree structure where there is only one root node. Nodes having both parent and child nodes are considered branch nodes while nodes having only parent nodes are leaf nodes. Loops or cycles in the physical topology are resolved into a logical topology that is acyclic and directed. A signaling scheme is developed in which nodes, via on board communications hardware, signal all connected nodes and respond accordingly until hierarchical relationships are established. Cycles are resolved by intelligently breaking links to yield an acyclic graph. Direction is established by each node recognizing its parent/child status with respect to connected nodes until a single node is established as a root node.

8. 发明公开

EP0674788A1 METHOD AND APPARATUS FOR ARBITRATING ON AN ACYCLIC DIRECTED GRAPH 失效
标题翻译：对非循环仲裁方法和装置向图。
公开(公告)号：EP0674788A1
公开(公告)日：1995-10-04
申请号：EP94905422.0
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： OPRESCU, Florin
IPC分类号： G06F13 , G06F15 , H04L12
CPC分类号： H04L12/40078 , G06F13/36 , G06F13/37 , G06F15/17343 , H04L12/40084 , H04L45/48
摘要： A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.

9. 发明授权

EP0679307B1 DELAY LINE SEPARATOR FOR DATA BUS 失效
标题翻译： VERZÖGERUNGSLEITUNGSSEPARATOR总线
公开(公告)号：EP0679307B1
公开(公告)日：2003-05-02
申请号：EP94909468.4
申请日：1994-01-12
申请人： APPLE COMPUTER, INC.
发明人： VAN BRUNT, Roger , OPRESCU, Florin
IPC分类号： H04L7/027 , G06F13/42
CPC分类号： H04L7/0066 , G06F13/423
摘要： The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as desired, to generate additional clock signals delayed by 5- or 10-nanosecond intervals.

10. 发明授权

EP0674789B1 METHOD AND APPARATUS FOR UNIQUE ADDRESS ASIGNMENT, NODE SELF-IDENTIFICATION AND TOPOLOGY MAPPING FOR A DIRECTED ACYCLIC GRAPH 失效
标题翻译：方法和设备，只有地址分配，节点的自我认同和拓扑图为目标，无环图
公开(公告)号：EP0674789B1
公开(公告)日：2003-03-19
申请号：EP94905423.3
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： OPRESCU, Florin
IPC分类号： G06F15/16
CPC分类号： H04L61/2038 , G06F13/36 , G06F15/17343 , H04L12/40078 , H04L29/12254 , H04L29/1232 , H04L45/48 , H04L61/2092
摘要： A node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an apriori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.

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