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1. 发明公开

EP1499978A4 METHOD AND APPARATUS FOR REDIRECTION OF OPERATIONS BETWEEN INTERFACES 有权转让
标题翻译：方法和设备对于操作端口之间的逆转
公开(公告)号：EP1499978A4
公开(公告)日：2007-03-07
申请号：EP03721791
申请日：2003-04-17
申请人： MIPS TECH INC
发明人： JAGD ANDERS , KINTER RYAN , INTRATER GIDEON
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3812 , G06F9/3802 , G06F9/3824 , G06F12/0848
摘要： A method and apparatus within a processing system (300) is provided for separating access to an instruction memory (312) and a data memory (314) to allow concurrent access by different pipeline stages (302) within the processing system (300) to both the instruction memory (312) and the data memory (314). An instruction memory interface (304) is provided to access the instruction memory (312). A data memory interface (306) is provided to access the data memory (314). Redirection logic is provided to determine whether an access by the data memory interface (306) should be directed to the instruction memory interface (304) utilizing either the address of the access, or the type of instruction that is executing.

2. 发明公开

EP1141821A4 PRIORITIZED INSTRUCTION SCHEDULING FOR MULTI-STREAMING PROCESSORS 审中-公开
标题翻译：基于优先级的调度命令的详细功耗处理器
公开(公告)号：EP1141821A4
公开(公告)日：2005-06-01
申请号：EP99966217
申请日：1999-12-13
申请人： MIPS TECH INC
发明人： NEMIROVSKY MARIO D , NEMIROVSKY ADOLFO M , SANKAR NARENDRA
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48
CPC分类号： G06F9/3851
摘要： A multi-streaming processor (14) has multiple streams (4) for processing multiple threads (1-3), and an instruction scheduler (5) including a priority record of priority codes (7, 8) for one or more of the streams (4). The priority codes (7, 8) determine in some embodiments relative access to resources (10-13) as well as which stream (4) has access at any point in time. In other embodiments priorities are determined dynamically and altered on-the-fly, which may be done by various criteria, such as on-chip processing statistics, by executing one or more priority algorithms, by input from off-chip (9), according to stream loading, or by combinations of these and other methods. In one embodiment a special code is used for disabling a stream, and streams may be enabled and disabled dynamically by various methods, such as by on-chip events, processing statistics, input from off-chip, and by processor interrupts. Some specific applications are taught, including for IP-routers and digital signal processors.

3. 发明公开

EP1386224A4 POLYNOMIAL ARITHMETIC OPERATIONS 审中-公开
标题翻译：多项式算术运算
公开(公告)号：EP1386224A4
公开(公告)日：2008-11-26
申请号：EP02706275
申请日：2002-02-15
申请人： MIPS TECH INC
发明人： STRIBAEK MORTEN , KISSELL KEVIN D , PAJLLIER PASCAL
IPC分类号： G06F7/72 , G06F9/38 , G06F7/00 , G06F7/38 , G06F7/556 , G06F7/60 , G09C1/00
CPC分类号： G06F7/724 , G06F7/725
摘要： Polynomial arithmetic instructions (3010) are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction (3013) are provided.

4. 发明公开

EP1257912A4 METHOD AND APPARATUS FOR IMPROVED COMPUTER LOAD AND STORE OPERATIONS 有权
标题翻译：方法和设备改进COMPUTERLADE-和存储操作
公开(公告)号：EP1257912A4
公开(公告)日：2006-12-20
申请号：EP01900915
申请日：2001-01-03
申请人： MIPS TECH INC
发明人： NEMIROVSKY MARIO , MUSOLL ENRIQUE , SANKAR NARENDRA , MELVIN STEPHEN
IPC分类号： G06F9/30 , G06F9/312 , G06F9/308 , G06F9/345 , G06F9/38 , G06F12/04
CPC分类号： G06F9/30018 , G06F9/30043 , G06F9/345 , G06F9/3851
摘要： Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address (13) in a memory (11) or a first register (17) in a register file (15) from whence to begin reading data entities, and a first address (13) or register (17) to begin storing the entities, and a number of entities to be read or written. In Masked Load and Masked Store operations (17, 18) stored masks are used to indicate patterns relative to the first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.

5. 发明公开

EP1299801A4 METHOD AND APPARATUS FOR IMPLEMENTING ATOMICITY OF MEMORY OPERATIONS IN DYNAMIC MULTI-STREAMING PROCESSORS 有权
标题翻译：方法和设备操作都必须在记忆原子动态多流处理器的实现
公开(公告)号：EP1299801A4
公开(公告)日：2005-08-24
申请号：EP01944671
申请日：2001-06-07
申请人： MIPS TECH INC
发明人： MELVIN STEPHEN , NEMIROVSKY MARIO D
IPC分类号： G06F9/52 , G06F9/38 , G06F9/46 , G06F9/00 , G06F12/14
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3851
摘要： A multi-streaming processor (711) has a plurality of streams (401) for streaming one or more instruction threads, a set of functional resources (107) for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism (813, 815, 817, 819) operating to set a lock when an atomic memory sequence is started and clear a lock when an atomic memory sequence is completed. In the preferred embodiments the lock mechanism comprises one or more storage locations (713) associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.

6. 发明公开

EP1379939A4 PARTIAL BITWISE PERMUTATIONS 有权
标题翻译：局部BITWISE排列
公开(公告)号：EP1379939A4
公开(公告)日：2008-08-20
申请号：EP02707785
申请日：2002-02-15
申请人： MIPS TECH INC
发明人： KISSELL KEVIN D , EKNER HARTIG W J , STRIBAEK MORTEN , JENSEN JAKOB SCHOU
IPC分类号： G06F9/305 , G06F7/00 , G06F9/30 , G06F9/308 , G06F7/38
CPC分类号： G06F9/30018 , C04B2237/366 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036
摘要： Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier. The array unit (3030) within the microprocessor or microcontroller includes two parallel multipliers (Marray 4100 and MParray 4200) and permutation logic (4300). The first array, Marray (4100), performs arithmetic multiplication. Marray (4100) uses Acc1 (3031) Acc2 (3032), M (3033) and sel (3034) as inputs and produces a ResultC and ResultS as outputs. The second array MParray 4200 performs binary polynomial multiplication. Permutation logic (4300) is used to perform various permutations on low order bits of RShold based on the value in RThold (3012).

7. 发明公开

EP1311947A4 INSTRUCTION FETCH AND DISPATCH IN MULTITHREADED SYSTEM 有权
标题翻译：阅读和-ABSENDUNG指令按某一多线程-SYSTEM
公开(公告)号：EP1311947A4
公开(公告)日：2008-02-27
申请号：EP01952463
申请日：2001-07-05
申请人： MIPS TECH INC
发明人： MUSOLL ENRIC , NEMIROVSKY MARIO D
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48
CPC分类号： G06F9/383 , G06F9/3804 , G06F9/3844 , G06F9/3851
摘要： In a multi-streaming processor, a system for fetching instructions from individual ones of multiple streams (stream 1, stream 2, stream s) to an instruction pipeline is provided, comprising: a fetch algorithm for selecting from which stream (stream 1, stream 2, stream s) to fetch an instruction, and one or more predictors for forecasting whether a load instruction will hit or miss the cache or a branch will be taken. The prediction or predictions are used by the fetch algorithm in determining from which stream to fetch, in some cases probabilities are determined and also used in decisions, and predictors may be used at either or both of fetch and dispatch stages.

8. 发明公开

EP1163591A4 PROCESSOR HAVING A COMPARE EXTENSION OF AN INSTRUCTION SET ARCHITECTURE 有权
标题翻译：处理器指令集架构的比较扩展模块
公开(公告)号：EP1163591A4
公开(公告)日：2006-03-22
申请号：EP00919300
申请日：2000-02-14
申请人： MIPS TECH INC
发明人： THEKKATH RADHIKA , UHLER G MICHAEL , HO YING-WAI , HARRELL CHANDLEE B
IPC分类号： G06F13/00 , G06T17/40 , G06F9/30 , G06F9/302 , G06F9/32 , G06F9/38 , G06T1/20 , G06T3/00 , G06T15/00
CPC分类号： G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/3885
摘要： A processor having a compare extension and a conditional branch extension (630) of an instruction set architecture (320) which incorporates a set of high performance floating point operations. The instruction set architecture (320) incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The compare extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and a paired-single floating point format. The conditional branch extension (630) includes instructions directed to branching if, for example, either one of the two condition codes (635) is false or true, if any of three condition codes (630) are false or true, or if any one of four condition codes (630) are false or true.

9. 发明公开

EP1192533A4 REGISTER TRANSFER UNIT FOR ELECTRONIC PROCESSOR 审中-公开
标题翻译：注册转移 - EINHEITFÜRELEKTRONISCHE PROZESSOREN
公开(公告)号：EP1192533A4
公开(公告)日：2005-06-08
申请号：EP99966218
申请日：1999-12-13
申请人： MIPS TECH INC
发明人： NEMIROVSKY MARIO D , NEMIROVSKY ADOLFO M , SANKAR NARENDRA
IPC分类号： G06F9/34 , G06F9/30 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48 , G06F9/24
CPC分类号： G06F9/462 , G06F9/30123 , G06F9/3851 , G06F9/461
摘要： A processing system has an instruction processor (IP) (1), register files (3 and 4) for storing data to be processed by the IP (1), such as a thread context, and a register transfer unit (RTU) (5) connected to the register files (3 and 4) and to the IP (1). Register files (3 and 4) may assume different states, readable and settable by both the RTU (5) and the IP (1). The IP (1) and the RTU (5) assume control of register files (3 and 4) and perform their functions partially in response to states for the register files, and in releasing register files (3 and 4) after processing, set the states. The invention is particularly applicable to multistreamed processors, wherein more register files (3 and 4) than streams may be implemented, allowing for at least one idle register file in which to accomplish background loading and unloading of data. The invention is also particularly applicable to processing systems dealing with real-time phenomena such as data packet processing in network routers.
摘要翻译：处理系统具有指令处理器（IP）（1），用于存储要由IP（1）处理的数据的寄存器文件（3和4），诸如线程上下文，以及寄存器传送单元（RTU）（5 ）连接到寄存器文件（3和4）和IP（1）。寄存器文件（3和4）可以采用不同的状态，可由RTU（5）和IP（1）读取和设置。 IP（1）和RTU（5）假定控制寄存器文件（3和4），并部分地执行它们的功能以响应寄存器文件的状态，并且在处理后释放寄存器文件（3和4）状态。本发明特别适用于多数据处理器，其中可以实现比流多的寄存器文件（3和4），从而允许至少一个空闲寄存器文件，其中完成后台数据的加载和卸载。本发明还特别适用于处理诸如网络路由器中的数据分组处理之类的实时现象的处理系统。

10. 发明公开

EP1290569A4 INTERSTREAM CONTROL AND COMMUNICATIONS FOR MULTI-STREAMING DIGITAL PROCESSORS 审中-公开
标题翻译：间物流控制和通信由于F R多重串流数字处理器
公开(公告)号：EP1290569A4
公开(公告)日：2005-05-11
申请号：EP00917917
申请日：2000-03-14
申请人： MIPS TECH INC
发明人： NEMIROVSKY MARIO D , NEMIROVSKY ADOLFO M , SANKAR NERENDRA
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F15/76 , G06F9/00 , G06F15/00 , G06F17/00
CPC分类号： G06F9/485 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/462 , G06F9/468
摘要： A multi-streaming processor has a plurality of streams (103) for streaming one or more instruction threads, a set of functional resources (107) for processing instructions from streams; and interstream control mechanisms (115) whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges.

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