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    • 4. 发明公开
    • Feed-forward compensation scheme for feedback circuits
    • 在反馈电路向前耦合补偿方案
    • EP1130769A3
    • 2008-07-23
    • EP01301603.5
    • 2001-02-22
    • Agere Systems Guardian Corporation
    • Gopinathan, VenugopalProdanov, Vladimir I
    • H03F1/32
    • H03F1/083
    • A feed-forward compensated negative feedback circuit comprises an operational amplifier (12) having an inverting and a non-inverting input and an output. A feedback element (16) is connected between the output of the operational amplifier and its inverting input to form a negative feedback loop. The inverting input of the op-amp is driven with a first transconductance amplifier (14) which produces an output current proportional to an input voltage. A feed-forward transconductance amplifier (30) receives the input voltage and produces an inverted output current proportional to the input voltage. A feed-forward current is injected at the output of the operational amplifier. By providing at the output of the op-amp the current it would be required to carry over the feedback loop, a voltage differential at the op-amp inputs is avoided, thus eliminating parasitic current flows across the parasitic input capacitance and thereby improving the circuits overall performance. In a second embodiment of the invention, a unity-gain buffer is included in the feedback loop to produce a unidirectional path. To reduce the power requirements of the buffer, a feed-forward current is injected at a point between the feedback impedance element and the unity-gain feedback buffer such that the buffer does not need to source any current through the impedance element.
    • 8. 发明公开
    • Field plated resistor with enhanced routing area thereover
    • 电阻随场板和布置在上方和扩展Leitweglenkungsgebiet
    • EP1184910A3
    • 2004-10-13
    • EP01307059.4
    • 2001-08-20
    • Agere Systems Guardian Corporation
    • Krutsick, Thomas J.
    • H01L29/8605H01L29/06H01L27/08H01L21/02H01L23/522
    • H01L29/66166H01L29/8605
    • An integrated circuit includes a field plated resistor having enhanced area thereover for routing metal conductors, formed in the same layer of metal as forms contacts to the resistor, is fabricated by a sequence of processing steps. A resistor having a resistor body and a contact region at each end thereof is formed in an active region of a semiconductor substrate. A first layer of insulative material is formed over the resistor and a window is created through the first layer of insulative material to the resistor body to form a first contact region. A layer of polysilicon is formed over the first insulative layer to define a field plate, the polysilicon field plate being contiguous with the first contact region of the resistor and extending over the resistor body to substantially to the other contact region, as layout, design, and fabrication rules permit. A second insulative layer is formed over the polysilicon layer. Windows are created in the second insulative layer to provide access to the polysilicon field plate and the second contact region. A metal layer is applied and unwanted metal is etched away to provide conductors over the polysilicon field plate of a field plated resistor having enhanced area thereover for routing metal conductors formed in the same layer of metal as forms contacts to the resistor.
    • 10. 发明公开
    • Boundary scan chain routing
    • 扫描的路由
    • EP1179740A3
    • 2004-01-07
    • EP01306739.2
    • 2001-08-07
    • Agere Systems Guardian Corporation
    • Goldovsky, Alexander
    • G01R31/3185
    • G01R31/318541G01R31/318538G01R31/318594
    • An integrated circuit includes a semiconductor die having a plurality of input/output pads. A plurality of boundary scan cells, one corresponding to each input/output pad, implements boundary scan functions associated with respective input/output pads. Each of the boundary scan cells includes a TDI input and a TDO output. The boundary scan cells are structured as a shift register to shift data from one boundary scan cell in a direction unilaterally to an adjacent boundary scan cell. A first boundary scan cell is the first boundary scan cell of the plurality of boundary scan cells to receive data. A last boundary scan cell is the last boundary scan cell of the plurality of boundary scan cells to receive data. An endless control conductor forms a loop proximate the plurality of boundary scan cells. The endless control conductor is coupled to each of the plurality of boundary scan cells to provide a test clock signal thereto. At least one other control conductor extends around the semiconductor die proximate the plurality of boundary scan cells. The at least one other control conductor is discontinuous between the first and last boundary scan cells. The invention can also be implemented at the system level.