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81. 发明公开

EP3923201A1 APPARATUS AND METHOD WITH NEURAL NETWORK 审中-实审
公开(公告)号：EP3923201A1
公开(公告)日：2021-12-15
申请号：EP21153747.7
申请日：2021-01-27
申请人： Samsung Electronics Co., Ltd.
发明人： KIM, Hyunsoo , KWON, Soonwan
IPC分类号： G06N3/04 , G06N3/06
摘要： A neural network-implementing neuromorphic device includes: a memory configured to store one or more instructions; an on-chip memory comprising a crossbar array circuit including synapse circuits; and one or more processors configured to, by executing instructions to drive a neural network, store binary weight values of the neural network in the synapse circuits, obtain an input feature map from the memory, convert the input feature map into temporal domain binary vectors, provide the temporal domain binary vectors as input values of the crossbar array circuit, and output an output feature map by performing, using the crossbar array circuit, a convolution computation between the binary weight values and the temporal domain binary vectors.

82. 发明公开

EP3899803A2 NEURAL NETWORKS IMPLEMENTED WITH DSD CIRCUITS 审中-公开
公开(公告)号：EP3899803A2
公开(公告)日：2021-10-27
申请号：EP19836747.6
申请日：2019-12-12
申请人： Microsoft Technology Licensing, LLC
发明人： STRAUSS, Karin , CEZE, Luis , LINDER, Johannes, Staffan, Anders
IPC分类号： G06N3/04 , G06N3/06 , G06N3/08

83. 发明公开

EP3889844A1 NEURAL NETWORK SYSTEM AND DATA PROCESSING TECHNOLOGY 审中-公开
公开(公告)号：EP3889844A1
公开(公告)日：2021-10-06
申请号：EP18944316.1
申请日：2018-12-29
申请人： Huawei Technologies Co., Ltd.
发明人： LIU, Zhe , ZENG, Zhong , WANG, Tieying , DUAN, Xiaoxiang , ZHANG, Huimin
IPC分类号： G06N3/06
摘要： This application provides a neural network system and a data processing method. The neural network system includes P computing units configured to perform an operation of a first neural network layer and Q computing units configured to perform an operation of a second neural network layer. The P computing units are configured to perform computing on first input data based on N configured first weights to obtain first output data after receiving the first input data. The Q computing units are configured to perform computing on second input data based on M configured second weights to obtain second output data after receiving the second input data. The second input data includes the first output data. A ratio of N to M corresponds to a ratio of a data volume of the first output data to a data volume of the second output data. The neural network system provided in this application can be applied to the artificial intelligence field, to improve data processing efficiency in a neural network system.

84. 发明公开

EP3874411A1 AN IMPROVED SPIKING NEURAL NETWORK 审中-公开
公开(公告)号：EP3874411A1
公开(公告)日：2021-09-08
申请号：EP19880608.5
申请日：2019-10-31
申请人： Brainchip, Inc.
发明人： VAN DER MADE, Peter AJ , MANKAR, Anil Shamrao
IPC分类号： G06N3/02 , G06N3/04 , G06N3/06 , G06N3/063 , G06N3/08 , G06N3/10 , G06N3/12

85. 发明公开

EP3857460A1 COMPOSITE BINARY DECOMPOSITION NETWORK 审中-公开
公开(公告)号：EP3857460A1
公开(公告)日：2021-08-04
申请号：EP18935853.4
申请日：2018-09-27
申请人： Intel Corporation
发明人： WANG, Zheng , LI, Jianguo , CHEN, Yurong
IPC分类号： G06N3/06

86. 发明公开

EP3855367A1 OPERATION ACCELERATOR, PROCESSING METHOD, AND RELATED DEVICE 审中-实审
公开(公告)号：EP3855367A1
公开(公告)日：2021-07-28
申请号：EP18936364.1
申请日：2018-10-09
申请人： Huawei Technologies Co., Ltd.
发明人： LIU, Hu , HUANG, Bin
IPC分类号： G06N3/06 , G06F17/16
摘要： An operation accelerator (10), a processing method, and a related device are provided. The operation accelerator includes: a first memory (102), configured to store an input dataset; a matrix converter (101), configured to perform the following actions: reading M row vectors from the input dataset, and generating a first instruction; and sending the M row vectors and the first instruction to a second memory (103); and the second memory (103), configured to perform, according to the first instruction, preprocessing on the M row vectors to obtain n row vectors, and store the n row vectors, where the n row vectors include the M row vectors and (n-M) padding row vectors, the n row vectors are N row vectors in a target matrix, and a storage sequence of the n row vectors in the second memory (103) is consistent with a sequence of the N row vectors in the target matrix. The operation accelerator (10), the processing method, and the related device can be used to improve efficiency of a convolution operation.

88. 发明授权

EP3138052B1 QUANTUM-ASSISTED TRAINING OF NEURAL NETWORKS 有权
公开(公告)号：EP3138052B1
公开(公告)日：2021-07-07
申请号：EP15723604.3
申请日：2015-05-01
发明人： ADACHI, Steven H. , DAVENPORT, Daniel M. , HENDERSON, Maxwell P.
IPC分类号： G06N10/00 , G06N3/04 , G06N3/06

89. 发明公开

EP3819772A1 METHOD FOR PRE-ALLOCATING MEMORY, THE ELECTRONIC DEVICE, AND THE COMPUTER PRODUCT 有权
公开(公告)号：EP3819772A1
公开(公告)日：2021-05-12
申请号：EP20206791.4
申请日：2020-11-10
申请人： Nextvpu (Shanghai) Co., Ltd.
发明人： PANG, Jun , CAI, Haijiao , FENG, Xinpeng , ZHOU, Ji
IPC分类号： G06F12/02 , G06F12/0873 , G06F12/0882 , G06N3/02 , G06N3/06
摘要： Provided are a method for pre-allocating memory, an electronic device, and a computer product. The method comprises: performing the following calculation operation for each successive layer of the neural network from a first layer of the neural network: attempting, for each output from a current layer, to obtain a memory block identifier from a list of idle memory block identifiers that is used to record idle memory block identifiers; if the memory block identifier is obtained, storing, as mapping relationship, an identifier of the output and the obtained memory block identifier into a mapping table of outputs and memory block identifiers, and deleting the memory block identifier from the list of idle memory block identifiers, wherein the mapping table of outputs and memory block identifiers is used to record an identifier of each output from the layer and the corresponding memory block identifier; or if the memory block identifier is not obtained, creating a new memory block identifier, storing, as mapping relationship, the identifier of the output and the new memory block identifier into the mapping table of outputs and memory block identifiers, and putting the new memory block identifier into a general list of memory block identifiers that is used to record all of the new memory block identifiers, for creating, according to the general list of memory block identifiers during the forward calculation for the neural network, a memory block required for the forward calculation for the neural network; and for each input to the current layer, putting, into the list of idle memory block identifiers, a memory block identifier corresponding to an output from a previous layer as the input if the output from the previous layer as the input is not used as an input to a subsequent layer of the current layer.

90. 发明公开

EP3770775A1 INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD 审中-实审转让
公开(公告)号：EP3770775A1
公开(公告)日：2021-01-27
申请号：EP18910335.1
申请日：2018-12-27
申请人： Sony Corporation , Sony Semiconductor Solutions Corporation
发明人： YOSHIYAMA, Kazuki , YAJIMA, Takumi , IKEGAYA, Ryoji
IPC分类号： G06F17/50 , G06N3/06
摘要： [Problem] To provide design support useful for hardware implementation of a neural network.
[Solution] Provided is an information processing device including a control unit that controls presentation of information related to an optimization structure when at least a part of a network structure of a designed neural network has been optimized for hardware processing. Provided is an information processing method including a step of controlling, by a processor, presentation of information related to an optimization structure when at least a part of a network structure of a designed neural network has been optimized for hardware processing.

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