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81. 发明授权

EP0528086B1 Verfahren und Anordnung zur Übermittlung von STM-vermittelten Nachrichten über ATM-Vermittlungsstellen 失效
标题翻译：方法和装置STM-介导的消息的上方的ATM交换机传输
公开(公告)号：EP0528086B1
公开(公告)日：1999-08-04
申请号：EP91307636.0
申请日：1991-08-19
申请人： SIEMENS AKTIENGESELLSCHAFT , MARCONI COMMUNICATIONS LIMITED
发明人： Schmidt, Lothar , Jugel, Alfred , Mallinson, Andy , Rau, Peter, Dr.
IPC分类号： H04L12/64
CPC分类号： H04Q11/0478 , H04J2203/0012 , H04J2203/0025 , H04L12/5601 , H04L12/6402 , H04L49/1553 , H04L49/3081 , H04L49/60 , H04L49/606 , H04L2012/5662 , H04L2012/6459

82. 发明公开

EP0931396A1 ASYNCHRONOUS TRANSFER MODE SWITCHING ARCHITECTURES HAVING CONNECTION BUFFERS 失效
标题翻译：交换架构对于异步连接缓冲区传输模式
公开(公告)号：EP0931396A1
公开(公告)日：1999-07-28
申请号：EP97946380.0
申请日：1997-10-28
申请人： Coreel Microsystems
发明人： PARRUCK, Bidyut , SANGHVI, Chetan, V. , BHASIN, Vinay, K. , DHARMAPURIKAR, Makarand , JOSHI, Uday, 23 Apruva Soc.
IPC分类号： G06T11 , H04L12
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L49/1576 , H04L2012/5635 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683
摘要： Improved methods and apparatus to facilitate switching Asynchronous Transfer Mode (ATM) cells through an ATM switching circuit (300) are disclosed. The improved methods and apparatus facilitate the implementation of per virtual connection buffering (302), per virtual connection arbitration (304) of ATM cells, and/or per virtual connection back-pressuring to improve switching efficiency and/or reduce the complexity and/or costs of the ATM switching circuit (300).

83. 发明授权

EP0750830B1 MODULAR STRUKTURIERTES ATM-KOMMUNIKATIONSSYSTEM 失效
标题翻译：模块化结构化ATM通信系统
公开(公告)号：EP0750830B1
公开(公告)日：1999-05-26
申请号：EP95912140.1
申请日：1995-03-15
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： HARTMANN, Siegfried , SCHRAMM, Heinrich , ROMBACH, Horst , LESCH, Hilmar
IPC分类号： H04Q11/04 , H04Q3/68
CPC分类号： H04Q3/685 , H04L49/104 , H04L49/1553 , H04L49/255 , H04L49/3081 , H04L2012/5625 , H04L2012/5652 , H04Q11/0478
摘要： An ATM communication system with a modular structure for transmitting packets of cells (Z) between ATM communication terminals (KE) through selective or fixed connections has a switching device (SB) and a remote control device (CB). An ATM coupling field module (ASN), at least one subscriber connection module (SLMP), a communication module (KM) and a synchronising module (TM) are arranged in the switching device (SB) and the control device (CB) consists of a personal computer (CB) that controls the operation, the transmission and the administration of the switching device (SB). A processor-controlled communication adapter (CA) is provided in the personal computer (CB) to ensure the exchange of information with the switching device (SB). This concept of a switching device (SB) and separate control device (CA) in a personal computer (PC) allows hardware and software to be largely uncoupled and to considerably increase the modularity and freedom of configuration of ATM communication systems (KS), in particular of small ATM communication systems.

84. 发明公开

EP0908040A1 SCALABLE HIGH PERFORMANCE SWITCH ELEMENT FOR A SHARED MEMORY PACKET OR ATM CELL SWITCH FABRIC 失效
标题翻译：扩展的高性能开关元件用于皮带领域常见的记忆调解包或ATM信元
公开(公告)号：EP0908040A1
公开(公告)日：1999-04-14
申请号：EP97915107.0
申请日：1997-03-05
申请人： LEVEL ONE COMMUNICATIONS, INC
发明人： VENKATARAMAN, Krishnan
IPC分类号： H04L12 , H04Q11
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/3081 , H04Q11/0478
摘要： A scalable high performance ATM cell/packet switch (HiPAS) element for a shared memory switch fabric application. The switch element includes a PAC Bus (Packet/ATM Cell Bus) and the Switch Fabric Controller Bus (SC Bus). The HiPAS switch element receives and transmits the ATM cells/packets through the PAC Bus. The PAC Bus provides independent parallel datapaths for the receive port and transmit port. The PAC Bus provides a unique structural feature to the HiPAS switch element and allows expansion to the switch capacity in a manner similar to a bit-slice processor. Multiple number of HiPAS switch elements can be concatenated to expand the capacity. In the concatenated configuration, the datapaths of the receive port and transmit port are interleaved so that the interconnection remains point-to-point. As the result, all of the switch ports in the switch execute the cell transactions concurrently on the PAC Bus. In addition, each switch fabric port has a dedicated serial port to exchange status information between the switch fabric and the switch port adapter.

85. 发明公开

EP0884876A1 Improvement packet switching 失效
标题翻译： Verbesserte Paketvermittlung
公开(公告)号：EP0884876A1
公开(公告)日：1998-12-16
申请号：EP98201768.3
申请日：1998-05-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Ren, Jing-Fei , Landry, Randall J. , Izzard, Martin John
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/1576 , H04L49/3081 , H04L2012/5672 , H04L2012/5681 , H04Q11/0478
摘要： A packet switch has N digital input ports (28) of bandwidth B for receiving data cells including destination addresses for determining output ports, a shared input cache (32), N memory modules of bandwidth N·B for buffering, a switch fabric, and N digital output ports. The digital multiplexer (30) receives each data cell from the input ports and writes it to the shared input cache together with a corresponding port queue number, queue position, & memory module number in response to its destination address so that (1) cells having the same queue number are cyclically assigned to different memory modules and (2) cells having the same queue position are cyclically assigned to different memory modules. The digital demultiplexer (34) reads each data cell from the shared input cache and writes it to one of the N memory modules according to its assigned memory module number and queue position. Then the switch fabric reads the data cells in each memory module by queue position and writes each to a corresponding output port matching the cell's queue number.
摘要翻译：分组交换机具有带宽B的N个数字输入端口（28），用于接收包括用于确定输出端口的目的地地址的数据单元，共享输入缓存（32），用于缓冲的N个带宽NB存储器模块，交换结构和N个数字输出端口。数字多路复用器（30）从输入端口接收每个数据单元，并响应于其目的地地址将其写入到共享输入缓存以及对应的端口队列号，队列位置和存储器模块号，使得（1）具有相同的队列号循环地分配给不同的存储器模块，并且（2）具有相同队列位置的单元被循环地分配给不同的存储器模块。数字解复用器（34）从共享输入高速缓存读取每个数据单元，并根据其分配的存储器模块编号和队列位置将其写入N个存储器模块中的一个。然后，交换结构通过队列位置读取每个存储器模块中的数据单元，并将其写入与单元的队列号匹配的相应输出端口。

86. 发明公开

EP0849916A2 Switching system comprising distributed elements allowing attachment to lines adapters 失效
标题翻译：包括分布式元件的交换系统，允许连接到线路适配器
公开(公告)号：EP0849916A2
公开(公告)日：1998-06-24
申请号：EP97480051.8
申请日：1997-08-19
申请人： International Business Machines Corporation
发明人： Blanc, Alain , Saurel, Alain , Brezzo, Bernard , Poret, Michel
IPC分类号： H04L12/56
CPC分类号： H04L49/3081 , H04L49/1553 , H04L2012/5642 , H04Q11/0478
摘要： A switching system comprising a switching structure (1130) for routing cells from a set of M input ports towards a set of M output ports. The systems further includes a set of distributed individual Switch Core Access Layer elements (S.C.A.L.) (1000) which communicating with one input and output port of the switching structure by means of a set of serial communication links (1400, 1600). Each SCAL element provides attachment to at least one Protocol Adapter (Protocol Engine 1600- 1900), and comprises a set of circuits (PINT 511-515; 611-614), each PINT circuit being associated with a corresponding one of said at least Protocol Adapter (Protocol Engine 1600-1900). The receive part of each circuit receives the data cells from the attached Protocol Adapter (Protocol Engine 1600) and includes at least one first FIFO storage (701-704) for storing the cells being received. Additionaly, there is introduced at least one extra byte to every cell, which at least one extra byte is reserved for a routing header dedicated for controlling either the routing process within the switching structure. Each transmit part of the destination PINT circuit comprises at least one second FIFO storage (801-802) having a substantially greater capacity than said of said first FIFO storage. Every Transmit part receives all the cells that are generated at the corresponding output port but uses the at least one extrabyte for determining whether or not the cell is to be entered into the at least second FIFO contained in a considered PINT circuit. Additionaly, each distributed individual SCAL element comprises control means for performing Time Division Multiplexing (TDM) access of the at least one first FIFO and second FIFO so that the high rate communication between the switching structure and SCALs can be distributed between the different Protocol Adapters. A set of serializer/deserializer permit the use of cheap serialized communication links between the centralized switching system and the different SCAL elements.
摘要翻译：一种交换系统，包括用于将来自一组M个输入端口的信元路由到一组M个输出端口的交换结构（1130）。这些系统还包括一组分布式的单独交换机核心接入层单元（S.C.A.L.）（1000），它借助一组串行通信链路（1400,1600）与交换结构的一个输入和输出端口进行通信。每个SCAL元件提供对至少一个协议适配器（协议引擎1600-1900）的附接，并且包括一组电路（PINT 511-515; 611-614），每个PINT电路与所述至少一个协议适配器（协议引擎1600-1900）。每个电路的接收部分从附加的协议适配器（协议引擎1600）接收数据信元并且包括至少一个用于存储正在接收的信元的第一FIFO存储器（701-704）。另外，每个单元至少引入一个额外字节，其中至少一个额外字节被保留用于专用于控制交换结构内的路由过程的路由头。目的地PINT电路的每个发送部分包括具有比所述第一FIFO存储器的容量大得多的容量的至少一个第二FIFO存储器（801-802）。每个发送部分接收在相应的输出端口产生的所有单元，但是使用至少一个额外字节来确定单元是否被输入到包含在所考虑的PINT电路中的至少第二FIFO中。另外，每个分布式单独的SCAL单元包括用于执行至少一个第一FIFO和第二FIFO的时分复用（TDM）接入的控制装置，使得交换结构和SCAL之间的高速通信可以在不同的协议适配器之间分配。一组串行器/解串器允许在集中式交换系统和不同的SCAL单元之间使用便宜的串行通信链路。

87. 发明公开

EP0587468A3 Réseau de connexion photonique permettant une diffusion 失效
标题翻译：具有多媒体能力的光电连接网络
公开(公告)号：EP0587468A3
公开(公告)日：1998-01-07
申请号：EP93402023.1
申请日：1993-08-06
申请人： ALCATEL N.V. , ALCATEL CIT , ALCATEL ITALIA S.p.A.
发明人： Masetti Francesco , Jacob Jean-Baptiste
IPC分类号： H04L12/18 , H04Q11/00
CPC分类号： H04L12/5601 , H04L49/1553 , H04L49/203 , H04L2012/5605 , H04Q11/0001 , H04Q11/0066
摘要： Pour permettre de diffuser un paquet de données d'une entrée (I1) vers plusieurs sorties (01, 02, 03, 06), le réseau de connexion comporte, dans chaque plan de commutation, au moins un étage (S2) constitué de commutateurs élémentaires (SE4, SE5, SE6) ayant au moins la capacité:
de router plusieurs exemplaires d'un paquet ayant été multiplié en amont (SE1); de multiplier un paquet, en le réémettant plusieurs fois successivement sur une même sortie; les exemplaires ainsi créés étant routés ensuite par les commutateurs élémentaires (SE7, SE8, SE9) d'un étage (S3) situé en aval. Application aux centres de commutation ATM photoniques.

88. 发明公开

EP0785699A2 Multicast routing in multistage networks 失效
标题翻译： Mehrfachsende-Leitweglenkung在mehrstufigen Netzen
公开(公告)号：EP0785699A2
公开(公告)日：1997-07-23
申请号：EP97300062.3
申请日：1997-01-07
申请人： AT&T Corp.
发明人： Chiussi, Fabio Massimo , Kumar, Vijay Pochampalli , Kneuer, Joseph George
IPC分类号： H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/1553 , H04L49/1576 , H04L49/203 , H04L49/3081 , H04L2012/5635 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681
摘要： Multicasting of an ingress cell received at one of a plurality of input ports is provided through a multistage switching network to one or more of a plurality of output ports. An ingress cell including a data payload and information identifying output ports of the network is received at one of the input ports of a first stage of the network. A determination is made of the minimum number of first output ports of the first stage of the network to which a single copy of the ingress cell is to be outputted to enable the ingress cell to reach all of the identified output ports. The single copy of the ingress cell is then routed to the minimum number of first output ports of the first stage of the network.
摘要翻译：在多个输入端口之一处接收的入口单元的组播通过多级交换网络提供给多个输出端口中的一个或多个。在网络的第一级的输入端口之一处接收包括数据有效载荷和识别网络的输出端口的信息的入口单元。确定要输出入口单元的单个副本的网络的第一级的第一输出端口的最小数量，以使得入口单元能够到达所有识别的输出端口。然后将入口单元的单个副本路由到网络第一级的最小数量的第一输出端口。

89. 发明公开

EP0589250A3 Verfahren zum Rundsenden von Zellen in einem im Asynchron-Transfer-Modus wirkenden Kommunikationsnetz 失效
标题翻译： ATM通信网络中的小区广播方法
公开(公告)号：EP0589250A3
公开(公告)日：1997-01-29
申请号：EP93113965.3
申请日：1993-08-31
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Hummel, Heinrich Dipl.-Math.
IPC分类号： H04L12/18 , H04L12/56
CPC分类号： H04L12/1854 , H04L12/5601 , H04L45/00 , H04L45/16 , H04L49/106 , H04L49/1553 , H04L49/203 , H04L2012/5652
摘要： Das erfindungsgemäße Verfahren bezieht sich auf ein Kommunikationssystem (KA) eines Kommunikationsnetzes (KN) bzw. eine Koppelstruktur (SN) eines Kommunikationssystems, bei dem bei rundzusendenden Zellen durch das Kommunikationsnetz (KN) bzw. die Koppelstruktur (SN) für jeden zusätzlichen Vermittlungspfad in jeder der Kommunikationssysteme (KA) bzw. Koppelstufen (ST) kommunikationssystem- bzw. koppelstufenspezifische Rundsendeinformationen (rsi) und daran angefügte weitere Routinginformationen (ri) gebildet und zusätzlich in einen Zellkopf (ZK) bzw. einen kommunikationssysteminternen Zellkopf (IZK) eingefügt werden. Mit Hilfe dieses Zellkopfes (ZK) bzw. kommunikationssysteminternen, der jeweiligen Zelle vorgesetzten Zellkopfes (IZK) werden die Zellen in dem Kommunikationsnetz (KN) bzw. der Koppelstruktur (SN) rundgesendet. Durch das erfindungsgemäße Verfahren bleibt das Selbststeuerungsprinzip von Zellen durch ein mehrstufiges Kommunikationsnetz (KN) bzw. eine n-stufige Koppelstruktur (SN) uneingeschränkt erhalten.

90. 发明公开

EP0750830A1 MODULAR STRUKTURIERTES ATM-KOMMUNIKATIONSSYSTEM 失效
标题翻译：模块化结构化ATM通信系统
公开(公告)号：EP0750830A1
公开(公告)日：1997-01-02
申请号：EP95912140.0
申请日：1995-03-15
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： HARTMANN, Siegfried , SCHRAMM, Heinrich , ROMBACH, Horst , LESCH, Hilmar
IPC分类号： H04Q3 , H04Q11 , H04L12
CPC分类号： H04Q3/685 , H04L49/104 , H04L49/1553 , H04L49/255 , H04L49/3081 , H04L2012/5625 , H04L2012/5652 , H04Q11/0478
摘要： An ATM communication system with a modular structure for transmitting packets of cells (Z) between ATM communication terminals (KE) through selective or fixed connections has a switching device (SB) and a remote control device (CB). An ATM coupling field module (ASN), at least one subscriber connection module (SLMP), a communication module (KM) and a synchronising module (TM) are arranged in the switching device (SB) and the control device (CB) consists of a personal computer (CB) that controls the operation, the transmission and the administration of the switching device (SB). A processor-controlled communication adapter (CA) is provided in the personal computer (CB) to ensure the exchange of information with the switching device (SB). This concept of a switching device (SB) and separate control device (CA) in a personal computer (PC) allows hardware and software to be largely uncoupled and to considerably increase the modularity and freedom of configuration of ATM communication systems (KS), in particular of small ATM communication systems.

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