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81. 发明授权

EP0306244B1 Fault tolerant computer system with fault isolation 失效
标题翻译：容错计算机系统故障遏制。
公开(公告)号：EP0306244B1
公开(公告)日：1995-06-21
申请号：EP88307964.2
申请日：1988-08-26
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Bruckert, William F. , Bissett, Thomas D. , Mazur, Dennis , Munzer, John , Bernaby, Frank , Bhatia, Jay H.
IPC分类号： G06F11/00 , G06F11/14 , G06F11/22
CPC分类号： G06F11/1633 , G06F11/0724 , G06F11/0727 , G06F11/076 , G06F11/079 , G06F11/10 , G06F11/1008 , G06F11/142 , G06F11/16 , G06F11/165 , G06F11/1658 , G06F11/20 , G06F11/2097 , G06F11/2205 , G06F2201/845
摘要： A fault tolerant computer system has a central processing system which includes at least one set of data pathways, and executes a series of data processing instructions including the transfer of messages along the plurality of data pathways. At least one set of transaction data storage devices are coupled to the data pathways for storing a predetermined number of successive messages transferred most recently on the data pathways. Error checking devices are included for detecting the presence of errors in the central processing system. Error storage devices are coupled to the transaction data storage devices and the error checking devices for causing the transaction data storage devices to cease storing additional messages in response to the detection of errors by the error checking device.

82. 发明授权

EP0384155B1 Kombination aus einem Medizintechnische Gerät mit redundant aufgebauter Steuereinheit zur Infusionstherapie oder Blutbehandlung und einem Programmiergerät 失效
标题翻译：用技术的医疗装置的组合冗余配置控制单元，用于输液治疗或血液处理，和编程装置。
公开(公告)号：EP0384155B1
公开(公告)日：1994-07-13
申请号：EP90101574.3
申请日：1990-01-26
申请人： B. Braun Melsungen AG
发明人： Steger, Jürgen, Dipl.-Ing , Seidel, Franz, Dipl.-Ing. , Heitmeier, Rolf, Dipl.-Ing.
IPC分类号： A61M5/172
CPC分类号： A61M5/172 , A61M1/16 , A61M2205/17 , G06F11/10 , G06F11/16

83. 发明公开

EP0398694A3 Fault tolerant data processing system 失效
标题翻译：容错数据处理系统
公开(公告)号：EP0398694A3
公开(公告)日：1994-02-02
申请号：EP90305307.2
申请日：1990-05-16
申请人： International Business Machines Corporation
发明人： Baker, Ernest Dysart , Dinwiddie, John Monroe, Jr. , Grice, Lonnie Edward , Joyce, James Maurice , Loffredo, John Mario , Sanderson, Kenneth Russell , Suarez, Gustavo Armando
IPC分类号： G06F11/16 , G06F9/44 , G06F15/16
CPC分类号： G06F11/1641 , G06F11/10 , G06F11/1008 , G06F11/1482 , G06F11/16 , G06F11/20
摘要： The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.
摘要翻译：两个虚拟操作系统（例如S / 370 VM，VSE或IX370和S / 88 OS）的功能合并为一个物理系统。 S / 88处理器的合作伙伴对运行S / 88操作系统，并处理系统的容错和单系统映像方面。一个或多个S / 370合作伙伴对直接通过S / 88总线连接到相应的S / 88处理器。每个S / 370处理器分配1到16兆字节的来自S / 88主存储器的连续存储器。每个S / 370虚拟操作系统认为其内存分配从地址0开始，并通过正常的S / 370动态内存分配和分页技术管理其内存。检查S / 370以防止S / 370访问S / 88存储空间。 S / 88操作系统是所有系统硬件和I / O设备的主人。在S / 370地址空间中的S / 88处理器直接响应S / 88应用程序，以便S / 88可以将I / O数据移入S / 370 I / O缓冲区并处理S / 370 I / O操作。 S / 88和S / 370对等处理器配对，可在单一系统环境中执行各自的操作系统，而无需重写任何操作系统。操作系统都不知道其他操作系统和其他处理器对。

84. 发明授权

EP0205101B1 Verfahren zum Betrieb einer Datenverarbeitungsanlage 失效
标题翻译：操作数据处理系统的方法
公开(公告)号：EP0205101B1
公开(公告)日：1993-09-22
申请号：EP86107637.0
申请日：1986-06-05
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Beck, Albert, Dipl.-Ing. , Block, Siegfried, Dipl.-Ing. , Burgard, Rolf, Dipl.-Ing. , Hanss, Karl, Dipl.-Ing.
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/16

85. 发明授权

EP0176464B1 Modular multi-channel clock synchronizer 失效
标题翻译：模块化多通道时钟同步器
公开(公告)号：EP0176464B1
公开(公告)日：1993-06-16
申请号：EP85630137.9
申请日：1985-08-29
申请人： UNITED TECHNOLOGIES CORPORATION
发明人： Tulpule, Bhalchandra R. , Oscarson, Edward M. , Vosgien, David J.
IPC分类号： G06F11/16 , G06F15/16
CPC分类号： G06F11/187 , G06F11/16 , G06F11/1604 , G06F11/1679 , G06F11/1691
摘要： A modular synchronizer for use in synchronizing individual signal processors in a multiprocessor system is disclosed. Each synchronizer has a counter for counting its assiciated processor's clock pulses and, upon reaching a selected count, providing a counter frame output signal at an output thereof for use by each of the other synchronizers in the system. Each synchronizer has a voter responsive to counter output signals from each of the other synchronizers, and from itself as well, at input ports thereof. Each synchronizer's voter provides a frame sync (macro sync) pulse in each counter frame after receiving a selected number of counter frame output signals from any of the synchronizers in the system. Each synchronizer's voted frame sync pulse is provided at an output port of the synchronizer and may be utilized, depending on the application, for routing back into the synchronizer at a frame sync input port for resetting the synchronizer at a frame sync input port for resetting the synchronizer's counter, or for routing to one or more (slave) synchronizers for the same purpose. Each synchronizer's voter includes a rising edge voter that arms a falling edge voter only during a selected portion of the expected counter frame period (voting window). The synchronizer voter architecture can include clocked latches or not. The synchronizer may include fast and slow clock detectors. The synchronizer interfaces with its associated processor and includes disable circuitry for permitting the CPU to disable nonfunctional frame sync signals.

86. 发明公开

EP0543825A1 EINRICHTUNG ZUR INTERRUPTVERTEILUNG IN EINEM MEHRRECHNERSYSTEM 失效
标题翻译：设备对于中断分布在多计算机系统。
公开(公告)号：EP0543825A1
公开(公告)日：1993-06-02
申请号：EP91911445.0
申请日：1991-06-03
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： GRONEMEYER, Michael
IPC分类号： G06F11
CPC分类号： G06F11/1691 , G06F11/16 , G06F11/1687 , G06F11/185
摘要： Dans un système d'ordinateurs m sur n, des signaux de synchronisation (TA, TB, TC) sont transmis sous forme de demandes d'interruption (IA, IB, IC) à des modules (BGA, BGB, BGC) dépendant des différents ordinateurs et de là à des portes majoritaires (MA, MB, MC) qui, lorsque la condition m sur n est respectée, déclenchent des interruptions correspondantes (INT2A, INT2B, INT2C) au niveau des ordinateurs correspondants. Pour pouvoir détecter, après la défaillance d'un ordinateur (par exemple MCA), l'absence de demandes d'interruption (IB) d'un autre ordinateur (par exemple MCB), chaque ordinateur encore en état de fonctionnement (MCB, MCC) provoque, à des intervalles plus longs, l'initialisation de programmes de contrôle pour la détection des défauts. Cette opération s'effectue par des liaison OU de signaux de synchronisation déterminés. La commutation des demandes d'interruption par les portes majoritaires nécessite bien moins de temps qu'une comparaison correspondante par logiciels et n'occasionne qu'une très faible charge de base du système informatique dans le traitement des interruptions.

87. 发明授权

EP0207611B1 Digital automatic flight control system with disparate function monitoring 失效转让
标题翻译：具有不同功能监控的数字自动飞行控制系统
公开(公告)号：EP0207611B1
公开(公告)日：1993-04-14
申请号：EP86303800.6
申请日：1986-05-19
申请人： HONEYWELL INC.
发明人： Davidson, Dale Dean , Endrud, Douglas Gene
IPC分类号： G06F15/50 , G06F11/16
CPC分类号： G06F11/16 , G05D1/0077

88. 发明公开

EP0440080A3 Fehlertolerantes Schieberegister auf der Basis neuronaler Netze 失效
标题翻译：基于神经网络的容错分离器
公开(公告)号：EP0440080A3
公开(公告)日：1993-03-10
申请号：EP91100801.9
申请日：1991-01-23
申请人： Daimler-Benz Aktiengesellschaft
发明人： Mohrdieck, Christian, Dr. rer. nat.
IPC分类号： G06F11/00 , G11C19/00 , G06F11/20
CPC分类号： G06F11/16 , G06N3/063
摘要： Die Erfindung betrifft ein fehlertolerantes Schieberegister mit einer bestimmten Anzahl von Ausgängen. Sie besteht darin, dass eine von der Anzahl n der Ausgänge abhängige Zahl von elektrischen bzw. elektronischen Bauelementen, die sigmoide Eingangs/Ausgangskennlinien aufweisen, in Zeilen und Spalten nach Art eines Gitters angeordnet sind. Dieses weist in Längsrichtung eine vorgebbare Zahl von Bauelementen und in Breitenrichtung eine vorgebbare Zahl von Bauelementen, also n aus jeweils p Spalten bestehenden Streifen zu je p r Stück Bauelementen auf. Zwischen den Bauelementen in einem Streifen sind synaptische Koppelungen vorgesehen.
摘要翻译：本发明涉及具有特定数目的输出的容错移位寄存器。它包括一个数字，取决于输出数量n，具有S形输入/输出特性的电气或电子部件，按行和列排列，如网格。在纵向上，后者具有规定数量的部件，并且在横向方向上是可分配数量的部件，也就是说，在每种情况下，在p个部件项目中，每个条带都有n个条带。在条带中的组件之间提供突触耦合。

89. 发明公开

EP0455442A3 Fault detection in link-connected systems 失效
标题翻译：链路连接系统中的故障检测
公开(公告)号：EP0455442A3
公开(公告)日：1992-11-04
申请号：EP91303838.6
申请日：1991-04-26
申请人： International Business Machines Corporation
发明人： Carusone, Anthony , Garrigan. Albert William , Hunsinger, Wayne , Moffitt, Gerald Thomas , Spencer, David Earl , Taylor, Jordan M.
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/2205 , G06F11/16
摘要： The invention relates to methods and apparatus for isolating faults in link-connected systems utilizing fault reports generated from within the system itself. The reports are transmitted to a central location, preferably during a predetermined time period, and are used to create a single error message identifying the probable nature and location of the fault. A preferred embodiment of the invention does not require either the construction or maintenance of systemwide configuration tables, commonly used performing fault location and analysis. Instead, each unit of a pair of link coupled units, initially or on reconnection, interrogates a link adapter at the other end of the link for an identifier that identifies both the remote unit and the remote link adapter. This "nearest neighbour" information is stored locally at each unit, and is transmitted to the central location when an error is detected. The nearest neighbour information, rather than information from a configuration table, may be used to combine multiple records relating to a fault event, locate the fault and diagnose its cause. Additionally, a preferred embodiment of the invention provides a plurality of reporting paths for each unit in the system, so that the failure of a given unit or link does not prevent error information from being communicated to the central location.

90. 发明公开

EP0415550A3 Apparatus and method for documenting faults in computing modules 失效
标题翻译：在计算机模块中记录故障的装置和方法
公开(公告)号：EP0415550A3
公开(公告)日：1992-05-27
申请号：EP90308008.3
申请日：1990-07-20
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Bruckert, William , Bissett, Thomas D. , Kovalcin, David , Ravi, Nene
IPC分类号： G06F11/22 , G06F11/16
CPC分类号： G06F11/2273 , G06F11/16
摘要： Method and apparatus for testing the operation of modules for use in a fault tolerant computing system that consists of two distinct computing zones. Diagnostic testing is performed when the system is powered on, the modules being subjected to module, zone and, if both zones are available, system diagnostic tests. Indications of faults detected during diagnostic testing are stored in an EEPROM on each module. Such fault indications can be cleared in the field by correcting the fault condition and successfully rerunning the diagnostic test during which the fault was detected. Indications of operating system detected faults are also stored in each module EEPROM. However, such fault indications are not field clearable.

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