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81. 发明公开

EP0604163A2 Transistor structure for improved base-collector junction characteristics 失效
标题翻译：晶体管结构可改善基极 - 集电极结特性
公开(公告)号：EP0604163A2
公开(公告)日：1994-06-29
申请号：EP93310311.1
申请日：1993-12-20
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Patel, Viren C,
IPC分类号： H01L29/73 , H01L29/06
CPC分类号： H01L29/0611 , H01L29/0615 , H01L29/1004
摘要： The present invention is directed to an improved base-collector junction transistor structure capable of higher junction breakdown voltages and lower junction capacitances than bipolar transistors of the prior art. A narrow trench (148) is used to positively affect junction breakdown voltage and junction capacitance. The trench (148) allows the beneficial characteristics of both depletion ring and mesa structures to be utilized. Depletion zone profiles that negatively affect junction breakdown voltage are minimized by using the trench (148) and a depletion enhancing channel (132).
摘要翻译：本发明涉及一种改进的基极 - 集电极结型晶体管结构，其能够比现有技术的双极型晶体管具有更高的结击穿电压和更低的结电容。窄沟槽（148）用于积极影响结击穿电压和结电容。沟槽（148）允许利用耗尽环和台面结构的有益特性。通过使用沟槽（148）和耗尽增强沟道（132），将对负极影响结击穿电压的耗尽区分布最小化。

82. 发明公开

EP0600750A2 Circuit assembly having interposer lead frame 失效
标题翻译：具有引线框插入片电路布置。
公开(公告)号：EP0600750A2
公开(公告)日：1994-06-08
申请号：EP93309726.3
申请日：1993-12-03
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hundt, Michael J.
IPC分类号： H01L23/64 , H01L23/495 , H01L25/16
CPC分类号： H01L23/49589 , H01L23/3107 , H01L23/49503 , H01L23/49838 , H01L23/49894 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48237 , H01L2224/48247 , H01L2224/49171 , H01L2924/01079 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/20753
摘要： A circuit assembly includes a finger lead assembly (12) having structure for supporting an interposer substrate assembly (14) and an electronic circuit device (16), the substrate assembly having conductive elements for providing electrical connection between finger leads (18) of the lead assembly (12) and respective circuit sections within the circuit device. The circuit device (16) is mounted proximate to an upper surface of the substrate assembly (14). At least one decoupling capacitor (52a,52b) is mounted on a lower surface of the substrate assembly (14) at a level below that of the finger leads (18) and electrically connected, through circuitry within the substrate assembly (14) including inter-level via connectors (88,92b), to respective circuits within the circuit device (16).

83. 发明公开

EP0596637A1 Input buffer circuit 失效
标题翻译： Eingangspufferschaltung。
公开(公告)号：EP0596637A1
公开(公告)日：1994-05-11
申请号：EP93308503.7
申请日：1993-10-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K17/161 , H03K19/00361
摘要： The present invention provides an input buffer circuit for reducing false transitions within a circuit. The input buffer circuit includes an input pad (10) for receiving an input voltage, an input buffer having an input and a circuit (12,14) for modifying a voltage (Vin) entering the input buffer to track changes in a power supply voltage (Vcc) relative to a voltage at the input pad (10). The circuit is connected in series between the input pad and the input the input buffer.
摘要翻译：本发明提供一种用于减少电路内的错误转换的输入缓冲器电路。输入缓冲电路包括用于接收输入电压的输入焊盘（10），具有输入的输入缓冲器和用于修改进入输入缓冲器的电压（Vin）的电路（12,14），以跟踪电源电压的变化（Vcc）相对于输入焊盘（10）处的电压。该电路串联连接在输入焊盘和输入缓冲器之间。

84. 发明公开

EP0595589A2 Differential output amplifier input stage with rail-to-rail common mode input range 失效
标题翻译：差分放大器的平衡输出与去在输入处的工作电压范围的共模范围。
公开(公告)号：EP0595589A2
公开(公告)日：1994-05-04
申请号：EP93308504.5
申请日：1993-10-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Ryat, Marc Henri
IPC分类号： H03F3/45
CPC分类号： H03F3/4521 , H03F3/45121 , H03F3/45529 , H03F2203/45028 , H03F2203/45126 , H03F2203/45212 , H03F2203/45232 , H03F2203/45366 , H03F2203/45402 , H03F2203/45711
摘要： An amplifier having a rail-to-rail common mode input range that can be used in low voltage power supply applications includes differential input and output stages, the output stage having first and second current paths. First and second output duplicating circuits are respectively connected in parallel with the first and second current paths in the differential output stage to duplicate the differential output. A circuit for detecting a common-mode voltage difference is provided between nodes of the first and second output duplicating circuits for developing a current related to the common-mode voltage difference. A current mirror circuit is connected to receive the current related to the common-mode voltage difference for controlling the current in the first and second current paths in the differential output stage. The circuit for detecting a common-mode voltage difference between nodes of the first and second output duplicating circuits can be established by a transistor that senses only common-mode current. The transistor has a control element connected to the nodes in the output duplicating circuits and a current path to a supply voltage.
摘要翻译：具有轨到轨共模输入范围的放大器可以用于在低电压电源应用确实包括差分输入级和输出级，其具有第一和第二电流路径的输出级。第一和第二输出复制电路被连接在分别与所述差分输出级复制的差动输出的第一和第二电流路径并联。用于开发的电流相关的共模电压差，第一和第二输出复制电路的节点之间提供了一种用于检测共模电压差电路。的电流镜电路被连接以接收电流相关的共模电压差，用于控制在所述第一和第二电流路径中的电流的差分输出级。由晶体管做感官仅共模电流可以建立用于检测所述第一和第二输出复制电路的节点之间的共模电压差的电路。该晶体管具有连接到输出复制电路和一个电流路径到电源电压的节点的控制元件。

85. 发明公开

EP0572161A3 AGC with non-linear gain for PLL circuits 失效
标题翻译： AGC为PLL电路提供非线性增益
公开(公告)号：EP0572161A3
公开(公告)日：1994-04-06
申请号：EP93303873.9
申请日：1993-05-19
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Carobolante, Francesco
IPC分类号： H03L7/107 , H03L7/095
CPC分类号： H03L7/095 , H03L7/107 , Y10S388/911 , Y10S388/912
摘要： A circuit automatically changes the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency, and a lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range. A circuit responsive to the sense signal output selectively applies the first frequency to clock the counter when the PLL is within the predetermined phase difference range, and to apply the second frequency to clock the counter when the PLL is operating outside of the predetermined phase difference range.
摘要翻译：电路自动改变PLL中的增益，以驱动具有表示电机旋转速度的电机速度信号类型的电机。该电路包括一个相位检测器，用于检测电动机速度信号与参考频率之间的相位差，并用于产生持续时间与检测到的相位差成比例的输出信号。计数器在输出信号的整个持续时间内对时钟脉冲进行计数，并且电机驱动电路响应于计数器达到的计数来驱动电机。时钟脉冲源在第一和第二频率处提供时钟信号，第二频率低于第一频率，并且锁定范围感测电路产生指示PLL何时处于预定相位差范围内的感测信号输出。当PLL处于预定相位差范围内时，响应于感测信号输出的电路选择性地施加第一频率以为计数器提供时钟，并且当PLL工作在预定相位差范围之外时施加第二频率以对计数器计时。

86. 发明公开

EP0586208A1 Output driver circuit 失效
标题翻译： Ausgangstreiberschaltung。
公开(公告)号：EP0586208A1
公开(公告)日：1994-03-09
申请号：EP93306836.3
申请日：1993-08-27
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles
IPC分类号： H03K19/003 , H03K19/017 , G11C7/02
CPC分类号： H03K19/00361
摘要： An output driver stage for an integrated circuit device includes slew rate control on the final logic gate. Slew rate control is provided by resistors (28,30,32,34) located in the power supply path for the gate (18,20). A switch (66,68,52,70) is connected in parallel across the resistor (28,30,32,34), and can be used to short the resistor (28,30,32,34) to disable or reduce slew rate limiting. The switch (66,68,52,70) is connected to another location within the output circuitry, and disables or reduces the slew rate limiting resistor (28,30,32,34) during a portion of the switching cycle. This provides for slew rate limiting during a portion of switching when it is most needed, and disables it when slew rate limiting is not required.
摘要翻译：用于集成电路器件的输出驱动器级包括在最终逻辑门上的转换速率控制。压摆率控制由位于门（18,20）的供电路径中的电阻（28,30,32,34）提供。开关（66,68,52,70）并联连接在电阻器（28,30,32,34）上，并且可以用于使电阻器（28,30,32,34）短路以禁止或减少转换速率限制。开关（66,68,52,70）连接到输出电路内的另一位置，并且在切换周期的一部分期间禁用或减小转换速率限制电阻（28,30,32,34）。这在最需要的时候提供了切换期间的转换速率限制，并且当不需要压摆率限制时禁止它。

87. 发明公开

EP0583991A1 Device for biasing an RF device operating in quasi-linear modes with temperature compensation 失效
标题翻译：装置用于与温度补偿的高频装置的准线性操作模式偏压工作。
公开(公告)号：EP0583991A1
公开(公告)日：1994-02-23
申请号：EP93306576.5
申请日：1993-08-19
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Rotay, Craig J.
IPC分类号： G05F3/22 , H03F1/30
CPC分类号： H03F1/302 , G05F3/225
摘要： A biasing device which is in thermal contact with an RF device for actively biasing the RF device operating in quasi-linear modes. The biasing device provides a low impedance current source with high current capability to the base of the RF device. The biasing device includes three specially-processed transistors. The second and third transistors are connected such that their base-emitter and base-collector junctions are in parallel effectively forming two exceptionally low turn on series diodes. The result of reducing the resistances of the second and third transistors, by configuration and processing, is that they turn on slightly before the RF device is biased to its quiescent point.
摘要翻译：偏压装置所有这些是在RF装置与热接触用于主动地偏置在准线性模式下操作所述RF设备。所述偏置装置提供具有高电流容量的RF装置的基座的低阻抗的电流源。偏置装置包括三个特殊处理的晶体管。第二和第三晶体管连接搜索做它们的基极 - 发射极和基极 - 集电极结是在平行有效地形成上串联二极管2个异常低的转弯。减少所述第二和第三晶体管的termoresistencias，通过配置和处理的结果，是GDP打开之前略微RF设备被偏置到其静态工作点。

88. 发明公开

EP0581608A1 Programmable difference flag logic 失效
标题翻译： Programmierbare Differenzflaggenlogik。
公开(公告)号：EP0581608A1
公开(公告)日：1994-02-02
申请号：EP93306052.7
申请日：1993-07-30
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles
IPC分类号： G06F5/06
CPC分类号： G06F5/06
摘要： Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.
摘要翻译：修改适用于FIFO存储器的差分标志逻辑，通过使用可编程的可复位计数器快速生成FIFO标志状态，从而无需减法器电路。比较器用于将读取计数器的值与写入计数器的值进行比较。通过将读取计数与写入计数相抵消等于所需FIFO标志值的值来代替减法器功能。通过使用提供可编程可重定位性的计数器来实现从写入计数读取计数的偏移。使用可编程的可复位计数器可以非常容易地选择和实现FIFO标志值。例如，用户可以从几乎完全的FIFO标志变为半完整的FIFO标志，而不改变任何硬件。计数器被简单地编程并相应地复位。

89. 发明公开

EP0581580A2 Gate drive circuit for a MOS power transistor 失效
标题翻译： Gate-Treiberschaltungfüreinen MOS-Leistung晶体管。
公开(公告)号：EP0581580A2
公开(公告)日：1994-02-02
申请号：EP93305948.7
申请日：1993-07-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hopkins, Thomas Lea R.
IPC分类号： H03K17/04 , H03K17/06
CPC分类号： H03K17/04123 , H03K17/063
摘要： An improved gate drive circuit for a MOS power transistor utilizes a dual gate drive circuit configuration. The first gate drive circuit operates to quickly turn on the MOS power transistor. After the MOS power transistor is turned on, the first gate drive circuit can be disabled. A second gate drive circuit is employed to provide continuous drive to the gate of the MOS power transistor to keep the MOS power transistor on.
摘要翻译：用于MOS功率晶体管的改进的栅极驱动电路利用双栅极驱动电路配置。第一栅极驱动电路用于快速接通MOS功率晶体管。在MOS功率晶体管导通之后，可以禁用第一栅极驱动电路。采用第二栅极驱动电路来向MOS功率晶体管的栅极提供连续驱动以保持MOS功率晶体管导通。

90. 发明公开

EP0547890A3 A read/write memory with interlocked write control 失效
标题翻译：具有互锁写控制的读/写存储器
公开(公告)号：EP0547890A3
公开(公告)日：1993-12-08
申请号：EP92311512.5
申请日：1992-12-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Iyengar, Narasimhan
IPC分类号： G11C7/00
CPC分类号： G11C7/22
摘要： A read/write memory, such as a static random access memory, is disclosed in which equilibration of differential data lines, such as bit lines or input/output lines, is performed at the beginning of each cycle. The memory includes a write circuit, for example associated with each sense amplifier, for driving the differential data lines with a data state corresponding to input data during a write operation. The write circuit is controlled by a write enable signal which, in this memory, is interlocked with the equilibration signal. As a result, the write operation is disabled during equilibration of the differential data lines. Since equilibration is maintained during address transitions, the write operation is only enabled during stable address periods, thus eliminating the possibility of a write to the address of a prior or subsequent cycle.
摘要翻译：公开了诸如静态随机存取存储器的读/写存储器，其中在每个周期开始时执行诸如位线或输入/输出线之类的差分数据线的平衡。存储器包括例如与每个读出放大器相关联的写入电路，用于在写入操作期间以对应于输入数据的数据状态来驱动差分数据线。写入电路由写使能信号控制，该写使能信号在该存储器中与平衡信号互锁。结果，在差分数据线的平衡期间禁止写入操作。由于在地址转换期间保持平衡，因此只能在稳定的寻址周期期间使能写操作，从而消除了写入先前或后续周期的地址的可能性。

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