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    • 81. 发明公开
    • HIGH-FREQUENCY LIMITER
    • 高频限制器
    • EP2161834A1
    • 2010-03-10
    • EP08765090.9
    • 2008-06-04
    • Furuno Electric Company, Limited
    • KOREYASU, MisaTAKASHIMA, Tetsuya
    • H03G11/00H01P1/15H01P5/103H01P7/04H03G11/02
    • H03G11/025H01P5/103H01P7/04
    • In order to provide a high-frequency limiter capable of absorbing variation in characteristic parameters of a PIN diode to acquire a desired limiting characteristic, an external re-entrant coaxial cavity is constituted by an external pedestal 15 and a cavity 34 inside a lower conductor part 13 and an upper conductor part 14, and an internal re-entrant coaxial cavity is constituted by an inner wall of the external pedestal 15 and by an internal pedestal 16 and a post 17. A PIN diode 18 is joined between the post 17 and the internal pedestal 16. Resonance windows 11 and 12 are provided between the resonator part and a waveguide connected thereto. A projected amount x of the external pedestal 15 with respect to the cavity 34 and an insertion amount y of the post 17 into the external pedestal 15 are adjustable independently. Further, a partition 30 is provided between each of the resonance parts 10 and 20 to form a coupling hole 60, and electromagnetic fields of the adjacent resonance parts 10 and 20 are made to be an even mode coupling, and thereby, the coupling hole 60 has a low-pass characteristic. Thus, generation of unnecessary resonance mode can be suppressed and a band expansion of a cutoff characteristic can be realized.
    • 为了提供能够吸收PIN二极管的特性参数变化以获得期望的限制特性的高频限制器,外部凹入同轴腔由外部基座15和下部导体部分内的腔体34构成 13和上部导体部分14组成,并且内部凹入同轴腔由外部基座15的内壁以及内部基座16和柱17构成.PIN二极管18连接在柱17和 内部基座16.共振窗口11和12设置在谐振器部分和与其连接的波导之间。 外部基座15相对于空腔34的突出量x和柱17插入外部基座15的插入量y可独立调节。 此外,在每个谐振部分10和20之间设置隔板30以形成耦合孔60,并且使相邻的谐振部分10和20的电磁场成为偶模耦合,从而耦合孔60 具有低通特性。 因此,可以抑制不需要的谐振模式的产生,并且可以实现截止特性的频带扩展。
    • 82. 发明公开
    • TDMA communications apparatus
    • TDMA-Kommunikationsvorrichtung
    • EP1662678A1
    • 2006-05-31
    • EP05257258.3
    • 2005-11-25
    • Furuno Electric Company, Limited
    • Hiraoka, Yasushi
    • H04B7/26
    • H04B7/2656H04W28/26H04W72/04H04W74/04
    • A CPU of a TDMA communications apparatus examines whether a slot to be allocated for a next transmission is a first slot (S1). If the slot to be allocated is the first slot, the CPU examines whether there are any slots already allocated by other stations within a Selection Interval SI in a frame in which the next transmission of own station is to be allocated referring to a slot map in a memory and finds out a free slot within Selection Interval SI (S11). Then, the CPU allocates the free slot as a next transmit slot of the own station and sets the slot number of the free slot as the slot number of the next transmit slot (S12). Then, the CPU examines whether a slot adjacent to the next transmit slot of the own station is allocated to any of the other stations (S13). If either of the slots adjacent to the next transmit slot of the own station is already allocated to another station, the CPU examines a time-out value set by that station for the adjacent slot (S15) and sets an initial time-out value differing from the time-out value set by the other station for the adjacent slot (S16).
    • TDMA通信装置的CPU检查要分配用于下一个传输的时隙是否是第一时隙(S1)。 如果要分配的时隙是第一时隙,则CPU检查是否存在已经由选择间隔SI内的其他站分配的任何时隙,在该帧中,将要分配本站的下一个传输参考时隙映射 存储器,并在选择间隔SI(S11)内找到空闲插槽。 然后,CPU分配空闲时隙作为本站的下一个发送时隙,并将空闲时隙的时隙号设置为下一个发送时隙的时隙号(S12)。 然后,CPU检查与本站的下一个发送时隙相邻的时隙是否被分配给任何其他站(S13)。 如果与本站的下一个发送时隙相邻的时隙中的任一个已经被分配给另一个站,则CPU检查该站为相邻时隙设置的超时值(S15),并设置不同的初始超时值 从相邻时隙的其他站设定的超时值(S16)。
    • 88. 发明公开
    • RADAR DEVICE AND METHOD FOR CHANGING RECEPTION GAIN OF RADAR DEVICE
    • EP3671258A1
    • 2020-06-24
    • EP18845858.2
    • 2018-07-31
    • Furuno Electric Company Limited
    • INOUE, Shuhei
    • G01S7/40G01S13/95G01W1/00
    • The disclosure provides a radar device capable of accurately and automatically calibrating nonuniformity of a gain caused by individual differences or temperature characteristics of components of a frequency conversion part. A radar device 1 includes a frequency conversion part 12 which converts a frequency of an echo signal obtained by reflecting a detection signal and receiving the reflected detection signal by an antenna 10, and amplifies a signal level thereof, within a period from a time when a transmission signal generation part 11 completes outputting a transmission signal to the antenna 10 to a time when a next one of the transmission signal starts to be output to the antenna 10. The radar device 1 includes a path switching part 20 which outputs, as a calibration signal, to the frequency conversion part 12, the transmission signal output by the transmission signal generation part 11 at a timing while the transmission signal is output to the antenna 10. A gain adjustment part 23 changes an amplification gain of the frequency conversion part 12 on the basis of a signal level of the calibration signal input to the frequency conversion part 12 and a signal level of the calibration signal having been amplified by the frequency conversion part 12.
    • 89. 发明公开
    • GRAPH GENERATING DEVICE
    • EP3594623A1
    • 2020-01-15
    • EP19185148.4
    • 2019-07-09
    • Furuno Electric Company Limited
    • OGAWA, Kenta
    • G01C21/32
    • A graph generating device (1) is provided, which may include an obstacle data acquiring module (11), a first graph generating module (21), a second graph generating module (31), and a graph synthesizing module (51). The obstacle data acquiring module (11) may acquire obstacle data including information on an obstacle (101, 102). The first graph generating module (21) may recursively subdivide an area (100) including the obstacle (101, 102) into cells by a quadtree dividing method, set a first vertex in an exclusive cell that is each of the cells without the obstacle (101, 102), and connect the first vertexes of the adjacent exclusive cells by a first side, to generate a first graph. The second graph generating module (31) may set second vertexes by a different method from the quadtree dividing method and connect the second vertexes by a second side, to generate a second graph. The graph synthesizing module (51) may generate a synthesized graph by synthesizing the first graph with the second graph.