专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明公开

EP1698055A1 CIRCUIT ARRANGEMENT AND METHOD FOR LOCKING ONTO AND/OR PROCESSING DATA, IN PARTICULAR AUDIO, TELEVISION AND/OR VIDEO DATA 审中-公开
标题翻译：电路装置及方法锁上及/或数据处理，包括音频，电视和/或视频数据
公开(公告)号：EP1698055A1
公开(公告)日：2006-09-06
申请号：EP04801468.2
申请日：2004-12-06
申请人： Philips Intellectual Property & Standards GmbH , Koninklijke Philips Electronics N.V.
发明人： MOEHLMANN, Ulrich, c/o Philips Intellectual Pty , SZAJ, Andreas, c/o Philips Intellectual Pty
IPC分类号： H03L7/087 , H03L7/113
CPC分类号： H03L7/107 , H03L7/085 , H03L7/087 , H03L7/093 , H03L2207/50 , H04N5/126
摘要： In order to further develop a circuit arrangement (100; 102; 104; 106) and a method of locking onto and/or processing data, in particular audio, T[ele]V[ision] and/or video data, by means of at least one phase locked loop (40), wherein phase information is detected by means of at least one phase detector (44), in particular following the arrival of at least one rising edge and/or falling edge of at least one analog input signal (50; 50'), at least one increment (24) is determined by means of at least one loop filter (30), to which the output signal (56) which is output by the phase detector (44) is fed, and at least one ramp oscillator (46) is fed the increment (24) which is output by the loop filter (30), such that inter alia the circuit arrangement (100; 102; 104; 106) and the method for operating the same can be readily adapted to various requirements, it is proposed that the phase locked loop (40) is essentially digital, wherein the input signal (50; 50'), in particular the phase of the input signal (50; 50') can be digitized by means of at least one time-to-digital converter (42), to which at least one system clock (52) is fed, the phase detector (44) is fed the output signal (54), in particular the additional phase information, of the time-to-digital converter (42) and also at least a first output signal (62a), in particular at least one status signal, of the ramp oscillator (46), and at least one frequency detector (48) is fed at least a second output signal (64), in particular at least one overflow pulse, of the ramp oscillator (46) and outputs frequency information (58) to the loop filter (30), which in particular is also assigned to at least one frequency locked loop (10).

72. 发明授权

EP0968568B1 EMULATING NARROW BAND PHASE-LOCKED LOOP BEHAVIOR ON A WIDE BAND PHASE-LOCKED LOOP 失效
标题翻译：窄带锁相环的行为上的宽频带移相LOOP EMULATION
公开(公告)号：EP0968568B1
公开(公告)日：2005-06-29
申请号：EP98911466.5
申请日：1998-03-04
申请人： LEVEL ONE COMMUNICATIONS, INC
发明人： EVERITT, James , PARKER, James
IPC分类号： H03L7/113

73. 发明公开

EP1274190A3 Time synchronisation system and method 审中-公开
标题翻译：系统和方法，用于时间同步
公开(公告)号：EP1274190A3
公开(公告)日：2004-09-29
申请号：EP02014519.9
申请日：2002-07-01
申请人： MOTOROLA, INC.
发明人： Miller, Peter
IPC分类号： H04J3/06 , H04L12/413 , B60R16/02 , H03L7/113 , G06F1/14 , H04L12/42
CPC分类号： H04J3/0685 , G06F1/10 , H04J3/0638 , H04L12/407 , H04L2012/40273
摘要： A time synchronisation system (4) and method for fault tolerant and time synchronisation distributed computing systems, for example, for use in automotive applications. The system (4) uses at least two nodes (2,3) in communication with at least one other node via a signal synchroniser (10), wherein each signal synchroniser detects frequency and phase errors in signals (28) generated from each oscillator (18) in the node (2,3), in comparison to the frequency and phase components of the received signal (20)generated by the oscillator (18) in the node sending the signal.

74. 发明公开

EP1229655A3 Phase locked loop apparatus 有权
标题翻译：具有一个锁相环装置
公开(公告)号：EP1229655A3
公开(公告)日：2004-04-28
申请号：EP02250528.3
申请日：2002-01-25
申请人： Marconi Mobile SpA
发明人： Pomona, Ignazio , Russo, Mario , Leonardi, Orazio
IPC分类号： H03L7/087 , H03L7/22 , H03L7/113 , H03L7/20
CPC分类号： H03L7/20 , H03L7/087 , H03L7/091 , H03L7/113
摘要： A phase locked loop apparatus 40 comprises an analogue phase locked loop 41 having a sampling phase detector 42 arranged to determine an error signal 44 corresponding to the phase difference between a reference frequency 43 and a frequency 50 generated by a voltage controlled oscillator 49. The error signal 44 is used in a feedback pathway 51 to control the frequency 50 generated by the voltage controlled oscillator 49 so as to reduce the error signal 44 over time. A second phase locked loop 53 comprises a digital phase locked loop unit 54 arranged to determine a direction indicator corresponding to the phase difference between the reference frequency 43 and the frequency 50 generated by the voltage controlled oscillator 49 and a microprocessor unit 55 that is arranged to vary the error signal 44 in a predetermined manner in accordance with the direction indicator until the value of the error signal 44 is within a predefined value range.

75. 发明授权

EP1221221B1 TAKT- UND DATENREGENERATOR FÜR UNTERSCHIEDLICHE DATENRATEN 有权
标题翻译：时钟和数据再生不同的数据速率
公开(公告)号：EP1221221B1
公开(公告)日：2003-05-02
申请号：EP00987020.5
申请日：2000-10-24
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： STILLING, Bernd , SOMMER, Jörg
IPC分类号： H04L7/033 , H04L25/02 , H03L7/113 , H03L7/087 , H03L7/14
CPC分类号： H03L7/113 , H03L7/087 , H03L7/197 , H04L7/0331 , H04L25/0262
摘要： Figure 1 shows the main block diagram of the inventive regenerator, which has a frequency control unit and a phase control unit. The phase control circuit (PLL) consists of a phase discriminator (PD), a loop filter, a controllable oscillator (5) and a frequency divider (6). Said frequency divider forms a clock pulse signal (TS) which is coupled back to a second input of the phase discriminator (PD). The data signal (DSF) is used as a reference signal. The aim of the invention is to provide a clock pulse and data regenerator that functions reliably and contiguously with different data signal bit rates. The regenerator should also be improved in such a way that differently coded data signals can be processed.

76. 发明公开

EP0989676A1 Frequency presetting device for a voltage controlled oscillator 审中-公开
标题翻译：压控振荡器的频率预设装置
公开(公告)号：EP0989676A1
公开(公告)日：2000-03-29
申请号：EP99307239.6
申请日：1999-09-14
申请人： TRT Lucent Technologies (SA)
发明人： Laffont, Jean
IPC分类号： H03L7/113
CPC分类号： H03L7/113 , H03L7/087
摘要： This invention relates to a frequency presetting device for a voltage controlled oscillator (VCO) including a servocontrol loop (ASS). This device is designed to preset the said voltage controlled oscillator (VCO) within a frequency range [f1, f2], where f1
Applications: coherent demodulation, Costas loops, etc.
摘要翻译：本发明涉及一种用于包括伺服控制回路（ASS）的压控振荡器（VCO）的频率预设装置。该设备被设计为在与所述振荡器的所述伺服控制回路的正确工作范围相对应的f1

77. 发明公开

EP0907252A2 Phase-locked loop with improved trade-off between lock-up time and power dissipation 有权
标题翻译：在锁定时间和功耗之间改进折衷的锁相环
公开(公告)号：EP0907252A2
公开(公告)日：1999-04-07
申请号：EP98118420.3
申请日：1998-09-29
申请人： SANYO ELECTRIC Co., Ltd. , Tottori Sanyo Electric Co., Ltd.
发明人： Sumi, Yasuaki Tottori Sanyo Electric Co., Ltd.
IPC分类号： H03L7/00 , H03L7/113 , H03L7/089 , H03L7/18
CPC分类号： H03L7/0891 , H03K23/665 , H03K23/68 , H03L7/087 , H03L7/113 , H03L7/18 , H03L7/181 , H03L7/191 , H03L7/1974 , H03L7/199
摘要： In a phase-locked loop with reference, feedback, and error signals, the trade-off between lock-up time and power dissipation is improved by one of the following methods: supplying a continuous error signal, instead of an intermittent error signal, to a charge pump during lock acquisition; employing a half-integer frequency divider and making multiple phase-and-frequency comparisons during each reference signal cycle; employing a prescaled feedback signal and making multiple phase-and-frequency comparisons during each reference signal cycle; providing multiple feedback loops and employing a selectable number of the loops during lock acquisition; and employing multiple feedback loops with prescaling of the reference and feedback signals.
摘要翻译：在带有参考电压，反馈电压和误差信号的锁相环中，通过以下方法之一可以改善锁定时间和功耗之间的折衷：向连续错误信号（而不是间歇错误信号）提供锁定采集期间的电荷泵; 采用半整数分频器并在每个参考信号周期中进行多个相位和频率比较; 采用预分频的反馈信号并在每个参考信号周期中进行多个相位和频率比较; 提供多个反馈回路并在锁定获取期间采用可选数量的回路; 并采用多个反馈环路对参考信号和反馈信号进行预分频。

78. 发明公开

EP0868030A1 Boucle à verrouillage de phase avec circuit d'assistance au verrouillage 失效
标题翻译： Phasenregelkreis mit Phasenregelhilfsschaltung
公开(公告)号：EP0868030A1
公开(公告)日：1998-09-30
申请号：EP98410031.3
申请日：1998-03-24
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Dufossez, Vincent
IPC分类号： H03L7/113
CPC分类号： H03L7/113 , H03D3/241
摘要： L'invention concerne une boucle à verrouillage de phase du type comprenant un circuit d'assistance au verrouillage (12) fournissant un signal de préréglage continu (IO) représentatif de la fréquence de porteuse d'un signal d'entrée (Fin) pour fixer la fréquence au repos d'un oscillateur commandé (16) de la boucle à verrouillage de phase. Le circuit d'assistance comprend une bascule monostable (40) cadencée par le signal d'entrée (Fin) pour fournir des impulsions (Im) de largeur prédéterminée (Tm), le signal de préréglage (IO) correspondant à la moyenne desdites impulsions.
摘要翻译：锁相环电路包括提供表示输入信号（Fin）的载波频率的连续预控信号（IO）的锁定辅助电路（12）。这用于在锁相环中固定受控振荡器（16）的静止频率。辅助电路包括同步驱动的单稳态触发器（40）。用输入信号（Fin）提供预定宽度（Tm）的脉冲（lm）。预控信号（IO）对应于这些脉冲的平均值。锁相环电路还包括用于与预控信号成比例地控制脉冲（lm）的振幅的晶体管（Q1，Q6），并用于与预控信号成反比地控制脉冲的宽度。

79. 发明公开

EP0768756A3 Receiver and frequency synthesizer-tuner for the same 失效
标题翻译：接收器和调谐为频率合成
公开(公告)号：EP0768756A3
公开(公告)日：1998-07-08
申请号：EP96116271
申请日：1996-10-10
申请人： PIONEER ELECTRONIC CORP
发明人： YAMAMAOTO YUJI , ICHIKAWA TOSHIHITO
IPC分类号： H03J1/00 , H03L7/113 , H03J5/02
CPC分类号： H03L7/113 , H03J1/005
摘要： An apparatus for acquiring tuning for a tuning frequency at a high speed is disclosed. In a receiver including a receiving unit (4) incorporating a VCO (4a), control section (2) and a tuning control unit (5), the tuning control unit holds the inputted tuning frequency information at the designated address in accordance with the storage designation signal supplied from said control unit and of controlling the oscillating frequency of the VCO based on the tuning frequency information held at the designated address in accordance with the read designation signal supplied from said control unit. This receiver can shorten the tuning time in exchanging the tuning frequency. Further, in a frequency synthesizer tuner comprising a frequency comparing means for acquiring a signal indicative of a frequency difference between a target tuning frequency and an oscillation frequency of VCO in a frequency comparison loop so that the tuning frequency is adjusted, a count time setting means (107,Fig.8) is provided for setting the count time for measuring the oscillating frequency of the VCO used by the oscillating comparison means, and the count time is increased whenever measurement of the oscillating frequency of the VCO is repeated by the frequency comparison means. This frequency synthesizer tuner can greatly shorten the time taken for the oscillating frequency of the VCO to coincide with the target tuning frequency.

80. 发明授权

EP0695478B1 A PHASE LOCK LOOP WITH ERROR CONSISTENCY DETECTOR 失效
标题翻译：的检测误差一致性锁相环
公开(公告)号：EP0695478B1
公开(公告)日：1997-08-20
申请号：EP94914218.6
申请日：1994-04-19
申请人： RCA THOMSON LICENSING CORPORATION
发明人： SAUER, Donald, Jon , RODDA, William , CAMPBELL, Edward, Richard, III , DELL'OVA, Francis
IPC分类号： H03L7/113
CPC分类号： H03B5/24 , H03B5/20 , H03B2200/0038 , H03B2200/005 , H03B2200/0058 , H03B2201/02 , H03B2201/025 , H03B2201/0266 , H03J2200/10 , H03L7/099 , H03L7/0991 , H03L7/113 , H03L7/14 , H04N5/126 , H04N7/122
摘要： A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected an the phase-lock-loop circuit operates in an idle mode of operation.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式