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71. 发明公开

EP2941773A1 ERASE FOR NON-VOLATILE STORAGE 有权转让
标题翻译：对消非易失性存储器
公开(公告)号：EP2941773A1
公开(公告)日：2015-11-11
申请号：EP13821341.8
申请日：2013-12-20
申请人： SanDisk Technologies Inc.
发明人： OOWADA, Ken , DUTTA, Deepanshu
IPC分类号： G11C16/34 , G11C16/14 , G11C16/04 , G11C11/56
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3418
摘要： Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the word lines may be held at a low voltage (e.g., close to OV). However, the voltage applied to an edge word may be increased in magnitude relative to a previous voltage applied to the edge word line for at least a portion of the sequence of erase voltages. The edge word line could be the word line that is immediately adjacent to the select line. The increasing voltage applied to the edge word line may prevent or reduce damage to oxides between the select line and edge word line. It may also help to regulate the e-field across a tunnel oxide of memory cells on the edge word line.

72. 发明公开

EP2586060A4 THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME 有权
标题翻译：三维存储器和方法进行训练吧
公开(公告)号：EP2586060A4
公开(公告)日：2015-08-12
申请号：EP11807258
申请日：2011-06-24
申请人： MICRON TECHNOLOGY INC
发明人： TANG SANH D , ZAHURAK JOHN K
IPC分类号： H01L27/115 , H01L21/28 , H01L21/8247 , H01L27/06 , H01L27/24 , H01L29/66 , H01L29/788 , H01L29/792 , H01L45/00
CPC分类号： H01L27/11582 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2213/71 , H01L21/28273 , H01L21/76838 , H01L23/528 , H01L27/0688 , H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/06
摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

73. 发明公开

EP2811527A2 Dual-mode transistor devices and methods for operating same 有权
标题翻译： Transistorvorrichtungen mit Zweifachmodus und Verfahren zu seinem Betrieb
公开(公告)号：EP2811527A2
公开(公告)日：2014-12-10
申请号：EP14153020.4
申请日：2014-01-29
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Lue, Hang-Ting , Chen, Wei-Chen
IPC分类号： H01L29/739 , H01L29/423
CPC分类号： H01L29/78645 , G11C16/0483 , G11C16/12 , G11C16/14 , G11C16/26 , H01L27/092 , H01L27/11568 , H01L29/4232 , H01L29/66484 , H01L29/7391
摘要： A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.
摘要翻译：双模式晶体管结构包括半导体本体。器件的半导体本体包括与沟道区的第一侧相邻的沟道区，p型端子区（可作为源极或漏极），以及邻近沟道区的n型端子区域（可用作源极或漏极）通道区域的第二侧。栅极绝缘体设置在沟道区域上的半导体本体的表面上。栅极设置在沟道区域上的栅极绝缘体上。第一辅助栅极设置在栅极的第一侧上，第二辅助栅极设置在栅极的第二侧上。可选地，可以在通道区域下方包括背栅。可以使用偏置辅助门来在单个设备中选择n通道或p通道模式。

74. 发明公开

EP2695196A2 SPEICHERZELLE 有权
公开(公告)号：EP2695196A2
公开(公告)日：2014-02-12
申请号：EP12729338.9
申请日：2012-03-29
申请人： Technische Universität Berlin
发明人： MARENT, Andreas , BIMBERG, Dieter
IPC分类号： H01L29/80 , B82Y10/00 , G11C16/04 , H01L29/788
CPC分类号： G11C16/0466 , B82Y10/00 , G11C16/0408 , G11C16/14 , G11C16/26 , H01L29/788 , H01L29/803
摘要： The invention relates, inter alia, to a memory cell (10) comprising at least one binary memory area for storing an item of bit information. According to the invention, it is provided that the memory area (SB) can optionally store holes or electrons and allows a recombination of holes and electrons, the charge carrier type of the charge carriers stored in the memory area defines the bit information of the memory area and a charge carrier injection device (PN) is present, by means of which optionally holes or electrons can be injected into the memory area (SB) and the bit information can thus be changed.
摘要翻译：本发明尤其涉及一种包括至少一个用于存储一位信息的二进制存储区的存储单元（10）。根据本发明提出，存储区（SB）可以可选地存储空穴或电子并允许空穴和电子的复合，存储在存储区中的电荷载流子的电荷载流子类型定义存储器的位信息区域和电荷载流子注入装置（PN），借助于该电荷载流子注入装置（PN），可选择地将空穴或电子注入存储区域（SB），并且因此可以改变位信息。

75. 发明公开

EP2620946A2 Adaptive programming and erasure methods for analog memory cells 审中-公开
标题翻译：自适应程序设计与自动化程序
公开(公告)号：EP2620946A2
公开(公告)日：2013-07-31
申请号：EP13152130.4
申请日：2013-01-22
申请人： APPLE INC.
发明人： Gurgi, Eyal , Kasorla, Yoav , Shalvi, Ofir
IPC分类号： G11C29/02 , G11C11/56 , G11C16/34
CPC分类号： G11C29/021 , G11C11/5628 , G11C11/5635 , G11C16/14 , G11C16/3445 , G11C16/3459 , G11C29/028 , G11C2029/0409
摘要： A method for data storage includes setting a group of analog memory cells to respective analog values by performing an iterative process that applies a sequence of pulses to the memory cells in the group. During the iterative process, a progress of the iterative process is assessed, and a parameter of the iterative process is modified responsively to the assessed progress. The iterative process is continued in accordance with the modified parameter.
摘要翻译：一种用于数据存储的方法包括：通过执行向该组中的存储器单元施加脉冲序列的迭代过程来将一组模拟存储器单元设置为各自的模拟值。在迭代过程中，迭代过程的进展被评估，并且迭代过程的参数响应于评估的进度而被修改。根据修改的参数继续迭代过程。

76. 发明公开

EP2599086A1 ELECTRONIC APPARATUSES 审中-公开
标题翻译：电子设备
公开(公告)号：EP2599086A1
公开(公告)日：2013-06-05
申请号：EP11748605.0
申请日：2011-07-26
申请人： Fujitsu Semiconductor Europe GmbH
发明人： LANDENBACH, Richard , WILLAM, Marc , STURM, Hartmut , DIEFFENBACH, Kai
IPC分类号： G11C16/10 , G11C16/16 , G06F12/02
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/064 , G06F2212/7207 , G11C16/102 , G11C16/105 , G11C16/14 , G11C16/16
摘要： Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event.
摘要翻译： 1。一种电子设备，包括：非易失性存储器（4），被配置为写入或读取在一次擦除扇区的存储器部分中，每个所述扇区（10）包括多个所述部分，并且所述存储器具有at 至少三个所述扇区，每个扇区适于彼此独立地擦除; 以及控制装置，用于控制扇区的擦除，其中：控制装置被配置为在除了目标之外的多个扇区中存储涉及擦除过程的所述扇区擦除信息，所述擦除过程涉及擦除目标扇区，可以检查扇区中的这种信息以在中断事件之后建立合适的恢复过程。

77. 发明公开

EP2586060A2 THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME 有权
标题翻译：三维存储器和方法进行训练吧
公开(公告)号：EP2586060A2
公开(公告)日：2013-05-01
申请号：EP11807258.6
申请日：2011-06-24
申请人： Micron Technology, INC.
发明人： TANG, Sanh, D. , ZAHURAK, John, K.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11582 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2213/71 , H01L21/28273 , H01L21/76838 , H01L23/528 , H01L27/0688 , H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/06
摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

78. 发明公开

EP2546837A1 Verfahren zum Erkennen von gelöschten Speicherbereichen 有权转让
标题翻译： Verfahren zum Erkennen vongelöschtenSpeicherbereichen
公开(公告)号：EP2546837A1
公开(公告)日：2013-01-16
申请号：EP12002829.5
申请日：2012-04-23
申请人： Giesecke & Devrient GmbH
发明人： Rankl, Wolfgang
IPC分类号： G11C16/14 , G06F12/02
CPC分类号： G11C16/14 , G06F12/0246 , G06F2212/177
摘要： Die Erfindung schafft ein Verfahren zur Fehleranalyse an einem in Speicherbereiche unterteilten elektronischen Speicher, insbesondere zum Erkennen von fälschlicherweise gelöschten Speicherbereichen in dem Speicher, z.B. einem in Speicherseiten (Pages) unterteilten Flash-Speicher. Das Verfahren umfasst die Schritte: a) Ermitteln einer Soll-Anzahl von gelöschten Speicherbereichen, b) Ermitteln einer Ist-Anzahl von gelöschten Speicherbereichen, c) Vergleichen der Ist-Anzahl und der Soll-Anzahl miteinander, und d) im Fall, dass die Ist-Anzahl und die Soll-Anzahl unterschiedlich sind, Erkennen, dass fälschlicherweise gelöschte Speicherbereiche existieren.
摘要翻译：该方法包括确定分区电子存储器（1）中的擦除存储器区域（2）的目标数量，并且通过对与存储区域的擦除状态相对应的存储器内容计数存储区域来确定擦除存储区域的实际数量。将擦除的存储区域的实际数量与擦除的存储区域的目标数量进行比较。如果擦除的存储区域的实际号码和目标号码不同，则会检测到未正确擦除的存储区域。确定擦除存储区域的识别标记，即页码。

79. 发明公开

EP2323164A3 Dense arrays and charge storage devices, and methods for making same 有权
标题翻译： Dichte matrizen und ladungsspeicheranordnungen und verfahren zur herstellung
公开(公告)号：EP2323164A3
公开(公告)日：2011-07-13
申请号：EP10011125.1
申请日：2001-08-13
申请人： SanDisk 3D LLC
发明人： Lee, Thomas H. , Cleeves, James M. , Subramanian, Vivek , Walker, Andrew J. , Petti, Christopher , Kouznetzov, Igor G. , Johnson, Mark G. , Farmwald, Paul M. , Herner, Brad
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L27/14 , G11C11/34 , H01L21/8246 , H01L21/336 , H01L21/84
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续器件级之间的至少一个表面平坦化。

80. 发明公开

EP2323164A2 Dense arrays and charge storage devices, and methods for making same 有权
标题翻译： Mehrebenen-Speichermatrix und deren Herstellungsverfahren
公开(公告)号：EP2323164A2
公开(公告)日：2011-05-18
申请号：EP10011125.1
申请日：2001-08-13
申请人： SanDisk 3D LLC
发明人： Lee, Thomas H. , Cleeves, James M. , Subramanian, Vivek , Walker, Andrew J. , Petti, Christopher , Kouznetzov, Igor G. , Johnson, Mark G. , Farmwald, Paul M. , Herner, Brad
IPC分类号： H01L27/115 , H01L29/788 , H01L27/14 , G11C11/34 , H01L21/8246 , H01L21/336 , H01L21/84
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续器件级之间的至少一个表面平坦化。

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