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61. 发明授权

EP0902482B1 SOI-MOSFET and fabrication process thereof 失效
标题翻译： SOI-MOSFET和方法及其生产
公开(公告)号：EP0902482B1
公开(公告)日：2003-09-17
申请号：EP98305138.4
申请日：1998-06-29
申请人： Sharp Kabushiki Kaisha
发明人： Adan, Alberto O.
IPC分类号： H01L29/786 , H01L29/10 , H01L21/336 , H01L21/265
CPC分类号： H01L29/66772 , H01L21/26586 , H01L29/78612

62. 发明公开

EP1155459A1 DEPLETION TYPE MOS TRANSISTOR 审中-公开
标题翻译： MOS耗尽型晶体管
公开(公告)号：EP1155459A1
公开(公告)日：2001-11-21
申请号：EP00990649.6
申请日：2000-12-04
申请人： Koninklijke Philips Electronics N.V.
发明人： EMMERIK, Arnoldus, J., M. , ZINGG, Rene, P. , VAN ZWOL, Johannes
IPC分类号： H01L29/808 , H01L29/10 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/1037 , H01L29/1058 , H01L29/78612
摘要： The invention relates to a SOI deep depletion MOS transistor provided in a thin silicon layer (5) adjoining a surface (4) of a silicon body (3) and insulated from a silicon substrate (7) by a buried oxide layer (6). The channel region (13) of a first conductivity type is provided with at least one and preferably a plurality of zones (16) of the opposite conductivity type adjoining the surface to remove minority carriers from the interface between the channel and the gate oxide (15). The zones (16) extend across the whole thickness of the channel and adjoin the buried oxide at the side of the channel remote from the gate dielectric. Due to this construction, minority carriers are removed also from the rear side of the channel. This enables the transistor to be operative also at high voltages having values at which the substrate and the buried oxide operate as a second gate and as a second gate dielectric, respectively. The transistor may be used to advantage in high-voltage ICs comprising a low-voltage circuit part operated with a low supply voltage generated by the transistor.

63. 发明公开

EP1143527A1 Semiconductor device of soi structure 有权
标题翻译： Halbleiterbauelement mit SOI-Struktur
公开(公告)号：EP1143527A1
公开(公告)日：2001-10-10
申请号：EP01302968.1
申请日：2001-03-29
申请人： SHARP KABUSHIKI KAISHA
发明人： Adan, Alberto O.
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/7841 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.
摘要翻译： SOI结构的半导体器件包括浮置状态的表面半导体层，其被堆叠在掩埋绝缘膜上，以构造SOI衬底，形成在表面半导体层中的第二导电类型的源/漏区，在源极/漏极区域之间的第一导电类型的沟道区域和通过栅极绝缘膜形成在沟道区域上的栅电极; 其中所述表面半导体层在其栅极宽度方向上在沟道区的至少一端处和/或附近形成有第一导电类型的势阱。

64. 发明公开

EP1045436A1 SEMICONDUCTOR DEVICE, SUBSTRATE FOR ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE, ELECTRONIC DEVICE, AND PROJECTION DISPLAY 审中-公开
标题翻译：半导体器件基板电光装置，电子光学装置，电子系统和投影显示设备
公开(公告)号：EP1045436A1
公开(公告)日：2000-10-18
申请号：EP99900034.2
申请日：1999-01-04
申请人： SEIKO EPSON CORPORATION
发明人： KAWATA, Hirotaka
IPC分类号： H01L21/336 , H01L29/786 , G02F1/133
CPC分类号： G02F1/136209 , G02F1/1368 , H01L29/78612 , H01L29/78633
摘要： The potential at a channel region of a MOSFET on a substrate needs to be stabilized to assure a drain withstand voltage. To this end, a new potential line is additionally required. However, the addition of the potential line causes a drop in the aperture ratio in a transmissive type liquid-crystal display device, in which lightness is particularly important. In the present invention, a light shielding layer overlapping the MOSFET formed on the substrate is electrically connected to the channel region in the MOSFET.
摘要翻译：需要稳定以确保漏极耐压在上衬底的MOSFET的沟道区的电位。为此，新的电位线，另外需要。然而，加入的电位线引起的开口率在透射型液晶显示装置的下降，其中明度是特别重要的。在本发明中，遮光层重叠而形成在基片上的MOSFET电连接到MOSFET的沟道区。

65. 发明公开

EP0902482A1 SOI-MOSFET and fabrication process thereof 失效
标题翻译： SOI-MOSFET和Verfahren zu dessen Herstellung
公开(公告)号：EP0902482A1
公开(公告)日：1999-03-17
申请号：EP98305138.4
申请日：1998-06-29
申请人： Sharp Kabushiki Kaisha
发明人： Adan, Alberto O.
IPC分类号： H01L29/786 , H01L29/10 , H01L21/336 , H01L21/265
CPC分类号： H01L29/66772 , H01L21/26586 , H01L29/78612
摘要： A SOI-MOSFET includes: a substrate (1); a buried oxide film (2) formed on the substrate; a top semiconductor layer (3) formed on the buried oxide film, said top semiconductor layer having a portion (5) of a first conductivity type; a gate electrode (4) formed on the top semiconductor layer with a gate oxide film (7) interposed therebetween; source and drain regions (13) of a second conductivity type formed in the top semiconductor layer and on both sides of the gate electrode; and an embedded region (6) of the second conductivity type which is disposed in the top semiconductor layer and between the source and drain regions and is separated from the source and drain regions and from an interface between the top semiconductor layer and the gate oxide film. The embedded region is defined by a tilted implantation of ions of the first conductivity type, using the gate electrode as a mask. The SOI-MOSFET has a fully depleted surface channel (5a) due to the contact potential between said surface channel and the embedded region, whereby the Kink effect is prevented.
摘要翻译： SOI-MOSFET包括：衬底（1）; 形成在所述基板上的埋入氧化物膜（2）形成在所述掩埋氧化膜上的顶部半导体层（3），所述顶部半导体层具有第一导电类型的部分（5）形成在上半导体层上的栅电极（4），其间插入有栅氧化膜（7）; 源极和漏极区域（13），形成在顶部半导体层中并在栅极电极的两侧; 以及第二导电类型的嵌入区域（6），其设置在顶部半导体层中并且在源极和漏极区域之间并且与源极和漏极区域以及从顶部半导体层和栅极氧化物膜之间的界面分离。通过使用栅电极作为掩模，倾斜注入第一导电类型的离子来限定嵌入区域。由于所述表面通道和嵌入区域之间的接触电位，SOI-MOSFET具有完全耗尽的表面通道（5a），从而防止扭结效应。

66. 发明公开

EP0638938A3 SOI transistor with improved source-high performance 失效
标题翻译： SOI晶体管具有高源改良剂。
公开(公告)号：EP0638938A3
公开(公告)日：1995-05-03
申请号：EP94202274.0
申请日：1994-08-08
申请人： PHILIPS ELECTRONICS N.V.
发明人： Merchant, Steven L., c/o Int.Octrooibureau B.V.
IPC分类号： H01L29/78 , H01L29/786 , H01L29/06 , H01L29/739 , H01L21/336
CPC分类号： H01L29/7824 , H01L29/0847 , H01L29/0886 , H01L29/402 , H01L29/42368 , H01L29/42384 , H01L29/66772 , H01L29/7393 , H01L29/7394 , H01L29/7813 , H01L29/78612 , H01L29/78624 , H01L29/861
摘要： The present application is directed to a thin film silicon SOI device having improved source-high performance especially for bridge-type circuits. The device prevents forward current saturation during such source-high operations, and is made by providing the drift region of a transistor with both a thicker and a thinner portion with reduced thickness over 1/3 to 2/3 of its length. Further a field plate is provided, which is separated from the gate electrode and extends over the thinner portion of the drift region. The gate electrode and field plate are short-circuited by a metal interconnect.

67. 发明授权

EP0373893B1 MOS type field effect transistor formed on a semiconductor layer on an insulator substrate 失效
标题翻译：在形成MOS场效应晶体管的绝缘基片上的半导体层。
公开(公告)号：EP0373893B1
公开(公告)日：1994-06-22
申请号：EP89312990.8
申请日：1989-12-12
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Yamaguchi, Yasuo c/o Mitsubishi Denki K.K. , Kusunoki, Shigeru c/o Mitsubishi Denki K.K.
IPC分类号： H01L29/08 , H01L29/52 , H01L29/32 , H01L29/784
CPC分类号： H01L29/0847 , H01L29/32 , H01L29/41733 , H01L29/78612 , H01L29/78621 , H01L29/78624
摘要： A SOI-MOSFET formed on a thin semiconductor layer (3) having a thickness not more than 1500 ANGSTROM includes a charge carrier absorbing region (9a, 9b, 9c) contacting with at least a portion of the bottom of a channel region (6) of a first conductivity type and with at least a portion of the bottom of a source region (7, 7a) of a second conductivity type. The carrier absorbing region (9a, 9b, 9c) absorbs excess carriers of the first conductivity type contained in the channel region (6).

68. 发明授权

EP0304811B1 MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：EP0304811B1
公开(公告)日：1993-05-26
申请号：EP88113464.7
申请日：1988-08-19
申请人： ASEA BROWN BOVERI AB
发明人： Svedberg, Per
IPC分类号： H01L29/78 , H01L27/12
CPC分类号： H01L29/78612 , H01L27/12

69. 发明公开

EP0497216A2 SOI transistor with pocket implant 失效
标题翻译： SOI晶体管Taschenimplantat。
公开(公告)号：EP0497216A2
公开(公告)日：1992-08-05
申请号：EP92101130.0
申请日：1992-01-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Houston, Theodore W. , Pollack, Gordon P.
IPC分类号： H01L29/784
CPC分类号： H01L29/66772 , H01L29/78612
摘要： A silicon-on-insulator MOS transistor (200) is disclosed that has an implanted region (32) of the same conductivity type as the body underneath one or both of the extended drain and source portions (26) of the drain (24) and the source (23) with and without a BTS contact or a general body contact. With only the pocket implants, the back gate threshold voltage is enhanced to reduce the possibility of back gate current flowing. With the pocket implants and a body contact, the floating body effects are minimized. Due to the BTS contact being located as far into the source as the pocket implant extends, negligible impact is made on the device channel. Ohmic connection between the source and the body is made for example by way of silicidation.
摘要翻译：公开了一种绝缘体上MOS晶体管（200），其具有与漏极（24）的延伸的漏极和源极部分（26）中的一个或两个相同的导电类型的注入区域（32）和具有和不具有BTS接触的源（23）或一般身体接触。仅使用袋式注入器，增加了背栅阈值电压，以减少背栅电流流动的可能性。随着口袋种植体和身体接触，浮体效应最小化。由于随着袋状植入物的延伸，BTS触点位于远处，因此对器件通道的影响可以忽略不计。源和身体之间的欧姆连接例如通过硅化法进行。

70. 发明公开

EP0480373A2 Thin-film semiconductor device 失效
标题翻译： Dünnfilm-Halbleiterunordnung。
公开(公告)号：EP0480373A2
公开(公告)日：1992-04-15
申请号：EP91117135.3
申请日：1991-10-08
申请人： SEIKO EPSON CORPORATION
发明人： Iwamatsu, Seiichi
IPC分类号： H01L29/784 , H01L29/60 , H01L29/62
CPC分类号： H01L29/78612 , H01L27/1203 , H01L29/0653 , H01L29/41733 , H01L29/78606 , H01L29/78639
摘要： Disclosed is a thin-film semiconductor device wherein a semiconductor thin-film (13) is formed on an insulating film (12) that has been formed on the surface of a semiconductor substrate (11) doped with a high-concentration active impurity and a semiconductor device is formed on the semiconductor thin-film. Thereby the electrical characteristics of thin-film semiconductor devices can be stabilized.
摘要翻译：公开了一种薄膜半导体器件，其中半导体薄膜（13）形成在已经形成在掺杂有高浓度有源杂质的半导体衬底（11）的表面上的绝缘膜（12）上，并且半导体器件形成在半导体薄膜上。从而能够稳定薄膜半导体器件的电气特性。

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