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51. 发明授权

EP1295448B1 CHANNEL EQUALIZER 有权
标题翻译：信道均衡器
公开(公告)号：EP1295448B1
公开(公告)日：2007-05-02
申请号：EP01945175.6
申请日：2001-05-21
申请人： Koninklijke Philips Electronics N.V.
发明人： WITTIG, Karl
IPC分类号： H04L25/03 , H04N5/21
CPC分类号： H04N5/211 , H04L25/03057 , H04L2025/03382 , H04L2025/03503 , H04L2025/03617 , H04L2025/03789
摘要： An adaptive channel equalizer with adaptive coefficients for compensating for long delays multipaths and distortions. A training sequence is periodically sent over the channel and the adaptive coefficients of the equalizer are periodically updated from the equalization of the transmitted training sequence. The equalization of the training sequence is performed separately and in parallel to the equalization of the remaining transmitted data by the equalizer.

52. 发明公开

EP1754353A1 A METHOD FOR SIGNAL PROCESSING AND A SIGNAL PROCESSOR IN AN OFDM SYSTEM 审中-公开
标题翻译：方法用于信号处理和信号处理器在OFDM系统
公开(公告)号：EP1754353A1
公开(公告)日：2007-02-21
申请号：EP05738594.0
申请日：2005-05-20
申请人： Koninklijke Philips Electronics N.V.
发明人： BAGGEN, Constant, P., M., J. , HUSEN, Sri, A. , STASSEN, Maurice, L., A. , TSANG, Hoi, Y.
IPC分类号： H04L25/03 , H04L27/26 , H04L25/02
CPC分类号： H04L25/022 , H04L25/03159 , H04L27/2647 , H04L2025/03414 , H04L2025/03496 , H04L2025/03503 , H04L2025/03611
摘要： A method of signal processing and a signal processor for a receiver for OFDM encoded digital signals. OFDM encoded digital signals are transmitted as data symbol subcarriers in several frequency channels. A subset of the sub-carriers is in the form of pilot subcarriers having a pilot value (ap) known to the receiver. The method comprises estimation of a channel transfer function (H) and a derivative of the channel transfer function (H’) by means of a channel estimation scheme from a received signal (y). Then, an estimation of data (a) is performed from the received signal (y) and the channel transfer function (H). Finally, an estimation of a cleaned received signal (y2) is performed from the data (a), the derivative of the channel transfer function (H') and the received signal (y) by removal of inter-carrier interference (ICI), by taking into account at least one of a previous and a future OFDM symbol, followed by an iteration of the above-mentioned estimations.

53. 发明公开

EP1604499A1 METHOD AND APPARATUS FOR REDUCING PHASE NOISE OF PHASE-ENCODED COMMUNICATION SIGNALS IN THE RECEIVER 审中-公开
标题翻译：的方法和装置相码通信信号的减少相位噪声RECEIVERS
公开(公告)号：EP1604499A1
公开(公告)日：2005-12-14
申请号：EP04708667.3
申请日：2004-02-05
申请人： Intel Corporation
发明人： KRAVTSOV, Vladimir
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L2025/03401 , H04L2025/0342 , H04L2025/03503
摘要： A receiver may reduce phase noise in phase-encoded communications signals using symmetrical averaging to estimate phase shift correction. In one embodiment, a receiver, such as a quadrature amplitude modulation receiver may include a decision feedback equalizer and a filter of low complexity to receive a phase modulated incoming signal. Using a combination of phase shift difference estimates prior and subsequent to a decision point for the received symbols, the filter may derive another estimate of the phase shift relative to the estimated phase shift by the equalizer.

54. 发明授权

EP1127423B1 MEASUREMENT OF NONLINEAR DISTORTION IN TRANSMITTERS 有权
标题翻译：测量非线性失真中站
公开(公告)号：EP1127423B1
公开(公告)日：2005-11-23
申请号：EP99971603.8
申请日：1999-11-02
申请人： Broadcom Corporation
发明人： CREIGH, John, L. , AGAZZI, Oscar, E.
IPC分类号： H04L1/24
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： The present invention provides a method for determining nonlinear distortion of a transmitter. A test symbol sequence is transmitted from the transmitter under test as an analog output signal. The analog output signal is sampled to produce a first sequence which represents the test symbol sequence as distorted by a linear distortion sequence and a nonlinear distortion sequence. The test symbol sequence is filtered via an adaptive filter to produce a second sequence such that the second sequence is approximately equal to the test symbol sequence as distorted by the linear distortion sequence. The second sequence is subtracted from the first sequence to produce an output sequence substantially equal to the nonlinear distortion sequence.

55. 发明授权

EP1129521B1 FIR FILTER STRUCTURE WITH LOW LATENCY FOR GIGABIT ETHERNET APPLICATIONS 有权
标题翻译：低延迟时间FIR滤波器结构用法千兆网卡
公开(公告)号：EP1129521B1
公开(公告)日：2005-06-01
申请号：EP99963876.0
申请日：1999-11-09
申请人： Broadcom Corporation
发明人： HATAMIAN, Mehdi
IPC分类号： H03H17/06 , H04B3/23 , H04B3/32 , H04L25/14 , H04L25/497 , H04L1/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method for reducing a propagation delay of a digital filter. The digital filter has an input path and an output path and includes a set of delay elements and a number of taps. The taps couples the input path to the output path. Each of the taps includes a coefficient, a multiplier and an adder. Each of the delay elements is disposed between two adjacent taps. The delay elements are placed in both the input path and the output path of the digital filter, such that the digital filter has fewer delay elements in the input path than a direct-form digital filter having the same number of taps in a direct-form structure and has fewer delay elements in the output path than a transposed-form digital filter having the same number of taps in a transposed-form structure, and such that the digital filter has same transfer function as the direct-form digital filter and the transposed-form digital filter.

56. 发明授权

EP1145024B1 DYNAMIC REGISTER WITH IDDQ TESTING CAPABILITY 有权
标题翻译：与测试休息消费能力的提升动态寄存器（DDQ）
公开(公告)号：EP1145024B1
公开(公告)日：2003-05-14
申请号：EP99960366.5
申请日：1999-11-12
申请人： Broadcom Corporation
发明人： HATAMIAN, Mehdi
IPC分类号： G01R31/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3012 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.

57. 发明公开

EP1262048A2 SYSTEM AND METHOD FOR HIGH SPEED COMMUNICATIONS USING DIGITAL SIGNAL PROCESSING 审中-公开
标题翻译：系统和方法与数字信号处理高速通信
公开(公告)号：EP1262048A2
公开(公告)日：2002-12-04
申请号：EP01955111.8
申请日：2001-02-28
申请人： Broadcom Corporation
发明人： AGAZZI, Oscar, E. , UNGERBOECK, Gottfried , PARHI, Keshab, K. , LUTKEMEYER, Christian, A., J. , VORENKAMP, Pieter , CHAN, Kevin, T. , WAKAYAMA, Myles, H.
IPC分类号： H04L25/03 , H04L25/497
CPC分类号： H04L25/4975 , H03M1/0604 , H03M1/1215 , H04L25/03133 , H04L25/03146 , H04L25/03343 , H04L25/497 , H04L2025/03503
摘要： Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

58. 发明公开

EP1233586A2 A method for channel equalization, a receiver, a channel equalizer, and a wireless communication device 审中-公开
标题翻译：一种用于信道均衡的方法，接收器，信道均衡器和无线通信设备
公开(公告)号：EP1233586A2
公开(公告)日：2002-08-21
申请号：EP01660229.4
申请日：2001-12-17
申请人： Nokia Corporation
发明人： Hämäläinen, Ari
IPC分类号： H04L25/02 , H04L25/03
CPC分类号： H04L25/03038 , H04L25/03063 , H04L2025/03401 , H04L2025/03471 , H04L2025/03503 , H04L2025/03611
摘要： The invention relates to a method for channel equalization in a receiver (2), in which a signal is received from a communication channel, the signal containing symbols ( S ( B l )) formed of binary information by phase shift keying. In the receiver, channel estimation is performed to estimate the properties of the communication channel, and samples are taken of the received signal at intervals. In the method, a determined number of samples is examined at the time, and a decision step is taken, in which, to find out the transmitted symbols ( S ( B l )), bit decisions (B) are computed on the basis of said determined number of samples. After each decision step, it is examined, whether said decision step is to be iterated. Upon iteration of said decision step, at least some of the bit decisions of the preceding decision step are used in addition to the samples under examination at the time, for computing the bit decisions.
摘要翻译：本发明涉及一种在接收器中（2），其中一个信号被从通信信道，通过相移键控形成的二进制信息的信号含符号（S（BL））接收到的信道均衡的方法。在接收机中，信道估计被执行以估计通信信道的属性，以及采样在时间间隔的接收信号的。在该方法中，将样品的确定性开采数在时间进行检查，判定步骤被采用，在其中，要找出反mitted符号（S（BL）），位决定（B）计算。所述的基础上确定性开采数量的样本。每个决策步骤之后，检查，是否所述判定步骤将被重复。当所述判定步骤的迭代中，至少一些所述preceding-判定步骤的比特决策都是在除了在样品时使用的被检查，用于计算所述比特决策。

59. 发明公开

EP1195021A2 PHY CONTROL MODULE FOR A MULTI-PAIR GIGABIT TRANSCEIVER 有权
标题翻译： PHY控制模块与几双千兆收发器
公开(公告)号：EP1195021A2
公开(公告)日：2002-04-10
申请号：EP00926364.1
申请日：2000-04-24
申请人： Broadcom Corporation
发明人： AGAZZI, Oscar E.
IPC分类号： H04L12/00
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/31715 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/0349 , H04L2025/03503 , H04L2025/03617
摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.

60. 发明公开

EP1145024A2 DYNAMIC REGISTER WITH IDDQ TESTING CAPABILITY 有权
标题翻译：与IDDQ测试能力动态REGISTER
公开(公告)号：EP1145024A2
公开(公告)日：2001-10-17
申请号：EP99960366.5
申请日：1999-11-12
申请人： Broadcom Corporation
发明人： HATAMIAN, Mehdi
IPC分类号： G01R31/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3012 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.

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