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    • 48. 发明公开
    • Video signal coding apparatus
    • Vorrichtung zur Videokodierung
    • EP0920212A2
    • 1999-06-02
    • EP98122010.6
    • 1998-11-19
    • Matsushita Electric Industrial Co., Ltd.
    • Fujiwara, YujiNishino, MasakazuTakeuchi, SeiichiWake, Kazuhiro
    • H04N7/26
    • H04N19/433H04N19/132H04N19/157H04N19/18H04N19/33
    • A video signal coding apparatus comprises a divider 102 that divides an input digital video signal into an effective area and an additional area, an effective-area blocking device 103 for dividing the effective area into effective blocks, an effective-area encoder 104 that hight-efficiency-codes the effective blocks to create effective compressed blocks, an additional-area encoder 105 that hight-efficiency-codes the additional area to create additional compressed data, an additional-area blocking device 106 for dividing the additional compressed data into additional compressed blocks each a luminance signal for a plurality of pixels and at least one color difference signal for pixels arranged at the same position as the plurality of pixels, and a substitution device 107 that substitutes the additional compressed blocks for data in the same effective compressed blocks at predetermined positions.
    • 视频信号编码装置包括将输入数字视频信号划分为有效区域和附加区域的分割器102,用于将有效区域划分为有效块的有效区域阻挡装置103,有效区域编码器104, 对有效块进行高效编码以创建有效的压缩块,附加区域编码器105,其高效编码附加区域以创建额外的压缩数据;附加区域阻塞装置106,用于将附加压缩数据划分为附加压缩块 每个用于多个像素的亮度信号和用于排列在与所述多个像素相同位置的像素的至少一个色差信号;以及替代装置107,将附加压缩块替换为预定的相同有效压缩块中的数据 位置。
    • 49. 发明公开
    • Image motion compensating address generator
    • 对于图像的运动补偿地址产生电路
    • EP0689358A3
    • 1998-04-29
    • EP95304060.7
    • 1995-06-13
    • LG ELECTRONICS INC.
    • Song, Gi Hwan
    • H04N7/36
    • H04N19/85H04N19/433H04N19/51
    • An image motion compensating address generator is disclosed including a mode selector for selecting a field mode or frame mode according to a video mode signal and a slice position signal, an address selection controller for controlling the generation of addresses according to the video mode signal and a motion coding type signal, a Y-direction read address generator for producing a Y-direction read address in units of processed block, an X-direction read address generator for dividing the processed block into four phases in the X direction and generating an X-direction read address, an X-direction write address generator for delaying the processed-block position signal and a field processed-block clock signal, and generating the X-direction write address of four phases, a Y-direction write address generator for producing a Y-direction write address, and a read & write controller for selectively outputting the X-direction and Y-direction read and write addresses according to a read/write selection toggle signal and an X-direction motion vector signal.