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41. 发明公开

EP0805559A2 Treiberstufe 失效
公开(公告)号：EP0805559A2
公开(公告)日：1997-11-05
申请号：EP97106966.1
申请日：1997-04-25
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Sommer, Diether, Dipl.-Phys. , Mitteregger, Gerhard , Savignac, Dominique, Dr.rer.nat. , Mukundarajan, Suraj
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： Die Erfindung betrifft eine Treiberstufe mit zwei Ausgangsfeldeffekttransistoren vom entgegengesetzten Leitungstyp, deren Laststrecken zwischen Versorgungsspannung und Masse geschaltet ist, wobei das Ausgangssignal am Knotenpunkt der Reihenschaltung der Laststrecken der beiden Feldeffekttransistoren abgreifbar ist,
wobei die Steueranschlüsse der Feldeffekttransistoren jeweils über die Laststrecke eines weiteren Feldeffekttransistors vom jeweils entgegengesetzten Leitungstyp mit dem Ausgang jeweils eines Spannungsreglers verschaltet sind und das zu treibende Signal dem Steueranschluß des weiteren Feldeffekttransistors zugeführt wird.
摘要翻译：场效应晶体管（2,3）的控制连接通过另外的互补FET（4,5）的导通路径连接到相应的电压调节器（6,7）的输出端。从每个调节器馈送脉冲发生器（8,9），并为每个输出FET的栅电极提供输出脉冲。由输入信号（1）寻址的隔离晶体管（10,11）分别设置在输出FET栅极和电源端子（14）和地之间。

42. 发明授权

EP0586208B1 Output driver circuit 失效
标题翻译：输出驱动电路
公开(公告)号：EP0586208B1
公开(公告)日：1997-10-29
申请号：EP93306836.3
申请日：1993-08-27
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles
IPC分类号： H03K19/003 , H03K19/017 , G11C7/02
CPC分类号： H03K19/00361

43. 发明授权

EP0574180B1 Balanced driver circuit for eliminating inductive noise 失效
标题翻译：用于抑制感应噪声对称驱动电路
公开(公告)号：EP0574180B1
公开(公告)日：1997-08-20
申请号：EP93304298.8
申请日：1993-06-03
申请人： AT&T Corp.
发明人： Rainal, Attilio Joseph
IPC分类号： H03K19/003
CPC分类号： H03K19/00361

44. 发明授权

EP0591750B1 Verfahren zur Stromeinstellung eines monolithisch integrierten Padtreibers 失效
标题翻译：一种用于单片集成焊盘驱动器的当前设置处理
公开(公告)号：EP0591750B1
公开(公告)日：1997-08-06
申请号：EP93115154.2
申请日：1993-09-21
申请人： Deutsche ITT Industries GmbH
发明人： Giebel, Burkhard, Dipl.-Ing.
IPC分类号： H03K19/003
CPC分类号： H03K17/166 , H03K19/00361

45. 发明公开

EP0785628A2 Transistor output circuit 失效
标题翻译：晶体管输出电路
公开(公告)号：EP0785628A2
公开(公告)日：1997-07-23
申请号：EP97100598.8
申请日：1997-01-16
申请人： CANON KABUSHIKI KAISHA
发明人： Sakuragi, Takamasa
IPC分类号： H03K19/003
CPC分类号： H03K19/00361 , H03K17/164
摘要： A transistor output circuit comprises a first insulated gate transistor having a control electrode connected to an input terminal, one main electrode connected to a first diode, and the other main electrode connected to a reference voltage source, and a second insulated gate transistor having a control electrode connected to the input terminal, one main electrode connected to an output terminal, and the other main electrode connected to the reference voltage source. A ratio (W 1 /L 1 ) of a gate width (W 1 ) to a gate length (L 1 ) of the first insulated gate transistor is larger than a ratio (W 2 /L 2 ) of a gate width (W 2 ) to a gate length (L 2 ) of the second insulated gate transistor.

46. 发明公开

EP0765037A2 Buffer for integrated circuit memories 失效
标题翻译：吹风机Speicherschaltungen
公开(公告)号：EP0765037A2
公开(公告)日：1997-03-26
申请号：EP96114778.2
申请日：1996-09-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coots, Timothy J. , Truong, Phat C. , Lin, Sung-Wei , Coffman, Tim M. , Robinson, Dennis R. , Syzdek, Ronald J.
IPC分类号： H03K19/0185 , H03K19/003
CPC分类号： H03K19/00384 , H03K19/00361
摘要： The circuit of this invention includes a current-compensated output buffer (OBC) that decreases the output switching rate as the conditions for transient noise increase to provide operation at maximum speed during worst-case speed conditions while suppressing noise during worst-case noise conditions. Transistors (M35-M42) in the output pre-driver stages (15,16) are used to limit the output-stage (14) charge and discharge rate. These limiting pre-driver transistors (M35-M42) are controlled by a supply-voltage (V CC ) and temperature compensating circuit (BGC). Compensating circuit (BGC) includes long channel transistors configured to increase a reference current (I REF ) with temperature and to decrease that reference current (I REF ) with increase in supply voltage (V CC ), the compensating circuit (BGC) providing biasing currents (I REFN and I REFP ) to output stage (14).
摘要翻译：本发明的电路包括电流补偿输出缓冲器（OBC），其随着瞬态噪声条件的增加而降低输出开关频率，以在最差情况下的速度条件下以最大速度运行，同时抑制最坏情况下的噪声条件下的噪声。输出预驱动级（15,16）中的晶体管（M35-M42）用于限制输出级（14）的充放电速率。这些限制性预驱动晶体管（M35-M42）由电源电压（VCC）和温度补偿电路（BGC）控制。补偿电路（BGC）包括配置为随温度增加参考电流（IREF）并随着电源电压（VCC）增加而减小该参考电流（IREF）的长沟道晶体管，补偿电路（BGC）提供偏置电流（IREFN和 IREFP）到输出级（14）。

47. 发明公开

EP0655177A4 BICMOS ECL-TO-CMOS LEVEL TRANSLATOR AND BUFFER. 失效
标题翻译： BiCMOS工艺ECL设为CMOS电平转换器和缓冲电路。
公开(公告)号：EP0655177A4
公开(公告)日：1997-03-26
申请号：EP93914239
申请日：1993-05-28
申请人： MICROUNITY SYSTEMS ENG
发明人： WONG BAN PAK
IPC分类号： H03K19/003 , H03K19/013 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/018521 , H03K19/00361 , H03K19/0136 , H03K19/017518
摘要： An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.

48. 发明公开

EP0739097A2 MOSFET circuit and CMOS logic circuit using the same 失效
标题翻译： MOSFET电路及其在CMOS逻辑电路中的应用
公开(公告)号：EP0739097A2
公开(公告)日：1996-10-23
申请号：EP96106128.0
申请日：1996-04-18
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： Douseki, Takakuni
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H03K19/0016 , H01L27/0218 , H03K19/00361
摘要： A MOSFET circuit achieving high speed operation and low power consumption for a wide supply voltage range. MOSFET circuits (111 and 112) are connected between a low threshold voltage CMOS circuit (3) and a supply voltage (VDD) and ground, as a power controller for switching power supply in response to sleep/active modes. High threshold voltage MOSFETs (M1 and M3) in the MOSFET circuits (111 and 112) are gate biased by low threshold voltage MOSFETs (M2 and M4), thereby preventing a current from flowing across the backgate terminal and the source terminal.

49. 发明授权

EP0398098B1 Output buffer for reducing switching induced noise 失效
标题翻译：输出缓冲级，以减少诱导的开关噪声
公开(公告)号：EP0398098B1
公开(公告)日：1996-10-02
申请号：EP90108489.7
申请日：1990-05-06
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Davis, Jeffrey B.
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/20
CPC分类号： H03K19/00361

50. 发明公开

EP0704972A3 Output circuit for gunning transceiver logic 失效
标题翻译：输出电路，用于所述类型的发射机/接收机逻辑“喷补”
公开(公告)号：EP0704972A3
公开(公告)日：1996-09-18
申请号：EP95115164.6
申请日：1995-09-26
申请人： NEC CORPORATION
发明人： Watarai, Seiichi
IPC分类号： H03K19/003
CPC分类号： H03K19/00361 , H03K19/018571
摘要： In a GTL circuit for restraining a ringing occurred by parasitic active elements on a package and a transmission path, the GTL circuits comprises two NMOS transistors connected in series to each other, for restraining a ringing between the gate and drain of an open drain type NMOS transistor which drives an output potential, and a plurality of delay circuits connected in series, for controlling periodically a current flowing through the two NMOS transistors, thereby reducing the ringing exceedingly the ringing caused by extremely large inductive elements which are connected to an output terminal as loads, and achieving a high speed operation of the GTL circuit.

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