专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明公开

EP2698807A4 METHOD FOR PRODUCING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：方法用于生产硅的半导体部件
公开(公告)号：EP2698807A4
公开(公告)日：2014-09-10
申请号：EP11863268
申请日：2011-09-09
申请人： SHINDENGEN ELECTRIC MFG
发明人： OHNO JUN-ICHI
IPC分类号： H01L21/04 , H01L21/28 , H01L21/3065
CPC分类号： H01L21/76889 , H01L21/0485 , H01L21/0495 , H01L21/3065 , H01L23/4827 , H01L29/1608 , H01L29/45 , H01L29/6606 , H01L29/66143 , H01L29/8611 , H01L29/872 , H01L2924/0002 , H01L2924/00

42. 发明公开

EP2656393A4 CONTACT RESISTANCE REDUCTION EMPLOYING GERMANIUM OVERLAYER PRE-CONTACT METALIZATION 有权转让
标题翻译：与锗层OVER预接触金属化接触电阻降低
公开(公告)号：EP2656393A4
公开(公告)日：2014-09-10
申请号：EP11852027
申请日：2011-09-30
申请人： INTEL CORP
发明人： GLASS GLENN A , MURTHY ANAND S , GHANI TAHIR
IPC分类号： H01L29/78 , H01L21/285 , H01L21/336 , H01L29/165 , H01L29/167 , H01L29/45 , H01L29/49 , H01L29/66
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in Sight of this disclosure, including both planar and non-planar transistor structures {e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type de vices, but can be used for n-type de vices if so desired.

43. 发明公开

EP2761663A1 ELECTROPOSITIVE METAL CONTAINING LAYERS FOR SEMICONDUCTOR APPLICATIONS 有权
标题翻译：除去方法正电金属，含有层半导体应用
公开(公告)号：EP2761663A1
公开(公告)日：2014-08-06
申请号：EP11873468.0
申请日：2011-09-29
申请人： Intel Corporation
发明人： ROMERO, Patricio E. , CLENDENNING, Scott B.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28556 , C23C16/30 , C23C16/42 , H01L21/28506 , H01L21/28562 , H01L21/28575 , H01L21/76843 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L29/04 , H01L29/0673 , H01L29/16 , H01L29/161 , H01L29/201 , H01L29/42392 , H01L29/45 , H01L29/49 , H01L29/4916 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/51 , H01L29/518 , H01L29/66522 , H01L29/66568 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 Å thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

44. 发明公开

EP2487709A4 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP2487709A4
公开(公告)日：2014-06-18
申请号：EP10821791
申请日：2010-07-30
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： TAMASO HIDETO , WADA KEIJI
IPC分类号： H01L21/28 , H01L21/336 , H01L29/16 , H01L29/78
CPC分类号： H01L21/0485 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7802

45. 发明公开

EP2722892A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：EP2722892A1
公开(公告)日：2014-04-23
申请号：EP12800187.2
申请日：2012-05-29
申请人： Sumitomo Electric Industries, Ltd.
发明人： HONAGA, Misako , MASUDA, Takeyoshi
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/12 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1608 , H01L29/45 , H01L29/4941 , H01L29/7811
摘要： A gate electrode (50) includes a polysilicon film (51) in contact with a gate insulating film (41), a barrier film (52) provided on the polysilicon film (51), a metal film (53) provided on the barrier film (52) and made of refractory metal. An interlayer insulating film (42) is arranged so as to cover the gate insulating film (41) and the gate electrode (50) provided on the gate insulating film (41). The interlayer insulating film (42) has a substrate contact hole (SH) partially exposing a silicon carbide substrate (30) in a region in contact with the gate insulating film (41). A interconnection (71) is electrically connected to the silicon carbide substrate (30) through the substrate contact hole (SH) and is electrically insulated from the gate electrode (50) by the interlayer insulating film (42).
摘要翻译：栅电极（50）包括与栅极绝缘膜（41）接触的多晶硅膜（51），设置在多晶硅膜（51）上的阻挡膜（52），设置在该阻挡膜上的金属膜（53）（52）并由难熔金属制成。层间绝缘膜（42）被布置为覆盖设置在栅极绝缘膜（41）上的栅极绝缘膜（41）和栅极电极（50）。层间绝缘膜（42）具有在与栅极绝缘膜（41）接触的区域中部分地暴露碳化硅衬底（30）的衬底接触孔（SH）。互连（71）通过衬底接触孔（SH）电连接到碳化硅衬底（30），并通过层间绝缘膜（42）与栅电极（50）电绝缘。

46. 发明公开

EP2486595A4 SEMICONDUCTOR DEVICE 有权
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP2486595A4
公开(公告)日：2014-04-16
申请号：EP10821866
申请日：2010-09-15
申请人： SEMICONDUCTOR ENERGY LAB
发明人： YAMAZAKI SHUNPEI , KOYAMA JUN , TAKAHASHI MASAHIRO , KISHIDA HIDEYUKI , MIYANAGA AKIHARU , NAKAMURA YASUO , SUGAO JUNPEI , UOCHI HIDEKI
IPC分类号： H01L29/786 , G02F1/1368 , G09F9/30 , H01L27/12 , H01L29/45 , H01L29/49 , H01L29/66
CPC分类号： H01L29/78669 , H01L27/1214 , H01L27/1225 , H01L27/124 , H01L27/1288 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78606 , H01L29/78678 , H01L29/7869
摘要： It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.
摘要翻译：本发明的目的是提供一种由具有良好显示质量的显示装置代表的半导体器件，其中在半导体层和电极之间的连接部分中产生的寄生电阻被抑制，并且具有不利影响，例如电压降，防止由于布线电阻而导致像素的信号布线，灰度级的缺陷等。为了实现上述目的，根据本发明的半导体器件可以具有这样的结构，其中具有低电阻的布线连接到薄膜晶体管，其中包括具有高氧亲和力的金属的源电极和漏电极是连接到具有抑制的杂质浓度的氧化物半导体层。此外，包括氧化物半导体的薄膜晶体管可以被要被密封的绝缘膜包围。

47. 发明公开

EP2715786A1 METAL OXIDE TFT WITH IMPROVED SOURCE/DRAIN CONTACTS 审中-公开
标题翻译：金属氧化物薄膜晶体管，改善源/漏极接触
公开(公告)号：EP2715786A1
公开(公告)日：2014-04-09
申请号：EP12796733.9
申请日：2012-05-16
申请人： CBrite Inc.
发明人： SHIEH, Chan-long , YU, Gang , FOONG, Fatt
IPC分类号： H01L21/36 , H01L21/44 , H01L21/465
CPC分类号： H01L29/7869 , H01L21/428 , H01L29/45 , H01L29/66969 , H01L29/78606
摘要： A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
摘要翻译：一种在金属氧化物半导体薄膜晶体管中形成欧姆源极/漏极接触的方法包括提供具有带隙的栅极，栅极电介质，高载流子浓度金属氧化物半导体有源层以及间隔开的薄膜晶体管薄膜晶体管配置。间隔开的源极/漏极金属触点在有源层中限定沟道区域。在沟道区域附近提供氧化环境，并且在氧化环境中加热栅极和沟道区域以降低沟道区域中的载流子浓度。可选地或附加地，每个源极/漏极接触件包括位于金属氧化物半导体活性层上的非常薄的低功函数金属层，并且具有高功函数金属的阻挡层位于低功函数金属上。

48. 发明公开

EP2711973A1 Al ALLOY FILM FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译： AL-LEGIERUNGSFILMFÜRHALBLEITERVORRICHTUNGEN
公开(公告)号：EP2711973A1
公开(公告)日：2014-03-26
申请号：EP12786105.2
申请日：2012-05-16
申请人： Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
发明人： OKUNO Hiroyuki , KUGIMIYA Toshihiro , YOKOTA Yoshihiro , MAEDA Takeaki
IPC分类号： H01L21/28 , C22C21/00 , C22F1/00 , C22F1/04 , C23C14/14 , C23C14/34 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53219 , C22C21/00 , C22C21/02 , C22C21/12 , C22C21/14 , C22F1/04 , C23C14/165 , C23C14/3414 , H01J37/3429 , H01L21/2855 , H01L29/16 , H01L29/1608 , H01L29/2003 , H01L29/45 , H01L29/452 , H01L2924/0002 , Y10T428/12431 , H01L2924/00
摘要： Provided is an Al alloy film for semiconductor devices, which has excellent heat resistance and is suppressed in the generation of hillocks even in cases where the Al alloy film is exposed to high temperatures, and which has low electrical resistivity as a film. The present invention relates to an Al alloy film for semiconductor devices, which is characterized by satisfying all of the features (a)-(c) described below after being subjected to a heat treatment wherein the Al alloy film is held at 500°C for 30 minutes and by having a film thickness from 500 nm to 5 µm. (a) The maximum grain diameter of the Al matrix is 800 nm or less. (b) The hillock density is less than 1x10 9 pieces/m 2 . (c) The electrical resistivity is 10 µΩcm or less.
摘要翻译：提供一种用于半导体器件的Al合金膜，其耐热性优异，并且即使在Al合金膜暴露于高温的情况下也能抑制小丘的产生，并且作为膜具有低的电阻率。本发明涉及一种用于半导体器件的Al合金膜，其特征在于，在将Al合金膜保持在500℃进行热处理后，满足下述所有特征（a） - （c） 30分钟，膜厚500nm〜5μm。（a）Al基体的最大粒径为800nm以下。（b）小丘密度小于1×10 9个/ m 2。（c）电阻率为10μΩcm以下。

49. 发明公开

EP2528100A4 CIRCUIT BOARD, DISPLAY DEVICE, AND PROCESS FOR PRODUCTION OF CIRCUIT BOARD 有权
标题翻译：板，显示装置及其制造方法BOARD
公开(公告)号：EP2528100A4
公开(公告)日：2014-03-12
申请号：EP10843931
申请日：2010-10-25
申请人： SHARP KK
发明人： HARA YOSHIHITO , NAKATA YUKINOBU
IPC分类号： H01L29/786 , G02F1/1368 , G09F9/30 , H01L21/28 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L23/52 , H01L27/12
CPC分类号： H01L21/02554 , H01L21/02565 , H01L27/1225 , H01L27/124 , H01L29/45 , H01L29/66969 , H01L29/7869

50. 发明公开

EP2698807A1 METHOD FOR PRODUCING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：EP2698807A1
公开(公告)日：2014-02-19
申请号：EP11863268.6
申请日：2011-09-09
申请人： Shindengen Electric Manufacturing Co., Ltd.
发明人： OHNO, Jun-ichi
IPC分类号： H01L21/28
CPC分类号： H01L21/76889 , H01L21/0485 , H01L21/0495 , H01L21/3065 , H01L23/4827 , H01L29/1608 , H01L29/45 , H01L29/6606 , H01L29/66143 , H01L29/8611 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a silicon carbide semiconductor device according to the present invention sequentially includes: a conductive layer forming step where a conductive layer is formed on a silicon carbide layer 110; a heat treatment step where the silicon carbide layer 110 and the conductive layer are made to react with each other thus forming an alloy layer formed of a reaction layer 120 which is in contact with the silicon carbide layer 110 and a silicide layer 124 which is present on the reaction layer 120; a first plasma ashing step where a carbon component which the silicide layer contains is removed; an etching step where at least a portion of the silicide layer 124 is removed using a hydrochloric acid, a nitric acid and a hydrofluoric acid thus exposing at least a portion of a surface of the reaction layer 120; and an electrode layer forming step where an electrode layer 130 is formed on an upper side of the exposed reaction layer 120. According to the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to manufacture silicon carbide semiconductor devices with high productivity, and also possible to overcome a drawback that dispersion in device characteristics occurs due to a silicon component remaining after an etching step.
摘要翻译：根据本发明的用于制造碳化硅半导体器件的方法依次包括：导电层形成步骤，其中在碳化硅层110上形成导电层; 使碳化硅层110和导电层彼此反应从而形成由与碳化硅层110接触的反应层120和存在的硅化物层124形成的合金层的热处理步骤在反应层120上; 第一等离子体灰化步骤，其中去除了硅化物层所含的碳成分; 蚀刻步骤，其中使用盐酸，硝酸和氢氟酸去除至少一部分硅化物层124，从而暴露反应层120的至少一部分表面; 以及电极层形成步骤，其中电极层130形成在暴露的反应层120的上侧。根据本发明的制造碳化硅半导体器件的方法，可以制造碳化硅半导体器件，其中生产率高，并且还可以克服由于在蚀刻步骤之后剩余硅成分而发生器件特性的分散的缺点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式