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41. 发明公开

EP0997781A1 Exposure method 审中-公开
标题翻译： Belichtungsverfahren
公开(公告)号：EP0997781A1
公开(公告)日：2000-05-03
申请号：EP99308452.4
申请日：1999-10-26
申请人： CANON KABUSHIKI KAISHA
发明人： Amemiya, Mitsuaki , Uzawa, Shunichi
IPC分类号： G03F7/20 , G03F1/14
CPC分类号： G03F7/7035 , G03F1/70 , G03F7/001 , G03F7/2022 , G03F7/70466
摘要： An exposure method for exposing a workpiece in a proximity exposure system, includes a first exposure step for printing, by exposure, an image of a first mask pattern on a predetermined portion of the workpiece, and a second exposure step for printing, by exposure, an image of a second mask pattern, different from the first mask pattern, on the predetermined portion of the workpiece, wherein exposures in the first and second exposure steps are performed superposedly, prior to a development process.
摘要翻译：一种用于在接近曝光系统中曝光工件的曝光方法包括：第一曝光步骤，用于通过曝光打印在工件的预定部分上的第一掩模图案的图像;以及第二曝光步骤，用于通过曝光打印，在工件的预定部分上的与第一掩模图案不同的第二掩模图案的图像，其中在显影处理之前，重叠地执行第一和第二曝光步骤中的曝光。

42. 发明公开

EP0997779A1 Exposure method and x-ray mask structure for use with the same 审中-公开
标题翻译： Belichtungsverfahren undRöntgenstrahlmaskedafür
公开(公告)号：EP0997779A1
公开(公告)日：2000-05-03
申请号：EP99308442.5
申请日：1999-10-26
申请人： CANON KABUSHIKI KAISHA
发明人： Chiba, Keiko , Uzawa, Shunichi , Amemiya, Mitsuaki , Watanabe, Yutaka
IPC分类号： G03F7/20 , G03F1/14
CPC分类号： G03F7/70325 , G03F1/22 , G03F1/50 , G03F7/001 , G03F7/2022 , G03F7/7035 , G03F7/70466
摘要： An exposure method for printing a pattern onto a workpiece to be exposed, includes a first exposure step for forming, on the workpiece and by exposure, a transferred image of a first absorbing material pattern formed on a mask and having no periodic structure, and a second exposure step for printing, on the workpiece and by exposure, a diffraction pattern to be produced through Fresnel diffraction due to a second absorbing material pattern formed on the mask and having a periodic structure, the diffraction pattern having a period corresponding to I/n of a period of the transferred image of the periodic structure pattern, where n is an integer not less than 2, and wherein the first and second exposure steps are performed simultaneously.
摘要翻译：一种用于将图案印刷到要曝光的工件上的曝光方法包括：第一曝光步骤，用于在工件上形成并且通过曝光形成在掩模上形成的并且不具有周期性结构的第一吸收材料图案的转印图像;以及第二曝光步骤，用于在工件上通过曝光在由掩模形成的具有周期性结构的第二吸收材料图案上通过菲涅耳衍射产生的衍射图案，所述衍射图案具有对应于I / n的周期的周期结构图案的转印图像的周期，其中n是不小于2的整数，并且其中第一和第二曝光步骤同时进行。

43. 发明公开

EP0907905A4 PROCESS FOR MODULATING INTERFEROMETRIC LITHOGRAPHY PATTERNS TO RECORD SELECTED DISCRETE PATTERNS IN PHOTORESIST 失效
标题翻译：方法，用于记录光刻胶DISCREET光刻图案通过调制干涉测量格局
公开(公告)号：EP0907905A4
公开(公告)日：1999-09-22
申请号：EP97927868
申请日：1997-06-10
申请人： HOLOGRAPHIC LITHOGRAPHY SYSTEM
发明人： HOBBS DOUGLAS S
IPC分类号： G03F7/00 , G03F7/20 , G03F7/26 , G03F7/38 , H01J9/02 , H01L21/027
CPC分类号： G03F7/70408 , G03F7/001 , G03F7/2022 , G03F7/265 , G03F7/38 , G03F7/70466
摘要： A double exposure process is disclosed whereby a first exposure produced by conventional photolithograpic techniques generates a latent negative image in a photoresist etch mask layer (22), the image subsequently employed to modulate a second exposure generated by the multiple beam interferometric lithography technique. Periodic surface relief structures (80) patterned by the second exposure and formed after development of the exposed photoresist material, are restricted to regions (52) defined by the initial exposure, with the photoresist material (54) outside these regions remaining unmodulated, or devoid of the periodic structures (80), and suitable for use as a mask in a subsequent etching process.

44. 发明公开

EP0907905A1 PROCESS FOR MODULATING INTERFEROMETRIC LITHOGRAPHY PATTERNS TO RECORD SELECTED DISCRETE PATTERNS IN PHOTORESIST 失效
标题翻译：方法，用于记录光刻胶DISCREET光刻图案通过调制干涉测量格局
公开(公告)号：EP0907905A1
公开(公告)日：1999-04-14
申请号：EP97927868.0
申请日：1997-06-10
申请人： Holographic Lithography Systems, Inc.
发明人： HOBBS, Douglas, S.
IPC分类号： G03F7 , H01J9 , H01L21
CPC分类号： G03F7/70408 , G03F7/001 , G03F7/2022 , G03F7/265 , G03F7/38 , G03F7/70466
摘要： A double exposure process is disclosed whereby a first exposure produced by conventional photolithograpic techniques generates a latent negative image in a photoresist etch mask layer (22), the image subsequently employed to modulate a second exposure generated by the multiple beam interferometric lithography technique. Periodic surface relief structures (80) patterned by the second exposure and formed after development of the exposed photoresist material, are restricted to regions (52) defined by the initial exposure, with the photoresist material (54) outside these regions remaining unmodulated, or devoid of the periodic structures (80), and suitable for use as a mask in a subsequent etching process.

45. 发明公开

EP0810474A3 Pattern exposing method using phase shift and mask used therefor 失效
标题翻译： Belichtungsverfahren mit Phasenverschiebung und Photomaske dazu
公开(公告)号：EP0810474A3
公开(公告)日：1998-12-16
申请号：EP97113132
申请日：1992-09-25
申请人： FUJITSU LTD
发明人： NAKAGAWA KENJI , KANAZAWA MASAO , HARUKI TAMAE , TABATA YASUKO
IPC分类号： G03F1/00 , G03F7/00 , G03F7/20
CPC分类号： G03F1/34 , G03F1/26 , G03F1/70 , G03F7/0035 , G03F7/2022 , G03F7/70283 , G03F7/70466
摘要： A pattern exposing method for forming a predetermined resist pattern (42) on a substrate (5). A resist layer (39) is exposed which is formed on the substrate (5) using a reticle (6) which includes a pattern for exposing a corresponding pattern on the resist layer by use of a phase shift of light transmitted through the reticle, the pattern of the reticle being defined by a phase shift layer (7) formed on a transparent reticle surface (2) and having first and second phase shift parts (7, 7A). The first phase shift part (7) has a width such that a closed ring pattern is exposed by the edge parts thereof, and the second phase shift part (7A) has a width narrower than that of the first phase shift part (7) so that patterns exposed by the edge parts thereof overlap in the form of a single line pattern. Then, the resist layer (39) is developed so that the predetermined resist pattern (42) is formed on the substrate (5).
摘要翻译：图案曝光方法通过使用包括第一掩模（6）的第一掩模（6）暴露形成在基板（5）上的第一抗蚀剂层（39）而在基板（5）上形成预定的抗蚀剂图案（41,42,42A）第一图案，用于通过使用透过第一掩模版的光的相移使第一抗蚀剂层上的第一对应图案曝光，使暴露的第一抗蚀剂层（39）显影，使形成在第一抗蚀剂层使用第二掩模版（6,14），包括第一抗蚀剂层（39）的顶部的基板（5）的整个表面，该第二掩模版具有用于通过使用光曝光在第二抗蚀剂层上的第二对应图案的第二图案透射通过第二掩模版，其中第二对应图案与第一对应图案的至少一部分重叠，并且使第二抗蚀剂层（40）显影，使得第一对应图案的一部分被第二对应图案和前置形成终止的抗蚀剂图案（41,42,42A）。

46. 发明授权

EP0561765B1 NOVEL METHOD OF MAKING, TESTING AND TEST DEVICE FOR INTEGRATED CIRCUITS 失效
标题翻译：用于生产以及测试的集成电路及测试装置集成电路
公开(公告)号：EP0561765B1
公开(公告)日：1998-12-02
申请号：EP89906938.9
申请日：1989-05-15
申请人： LEEDY, Glenn J.
发明人： LEEDY, Glenn J.
IPC分类号： G01R1/06
CPC分类号： G01R31/31912 , G01R1/07307 , G01R1/0735 , G01R31/2831 , G03F7/70466 , G03F7/70658 , G11C29/006 , H01L22/22 , H01L2924/15192 , Y10T29/4913 , Y10T29/49155 , Y10T29/49764
摘要： Each transistor or logic unit on an integrated circuit wafer (1) is tested prior to interconnect metallization. By CAD means, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD means. Each die in the wafer (1) thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface (10) made in one embodiment or several layers of flexible silicon dioxide (104), each layer containing vias (116) and conductive traces (17) leading to thousands of microscopic metal probe points (15) on one side of the test surface. The probe points electrically contact the contacts (2) on the wafer (1) under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.

47. 发明授权

EP0811181B1 VERFAHREN UND VORRICHTUNG ZUM STRUKTURIEREN EINER PHOTOLITHOGRAPHISCHEN SCHICHT 失效
标题翻译：用于构造光刻层的方法和装置
公开(公告)号：EP0811181B1
公开(公告)日：1998-09-09
申请号：EP96914126.6
申请日：1996-04-25
申请人： FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
发明人： PAUFLER, Jörg , SELTMANN, Rolf , KÜCK, Heinz
IPC分类号： G03F7/20
CPC分类号： G03F7/70466 , G03F7/70291

48. 发明授权

EP0515577B1 MAKING AND TESTING AN INTEGRATED CIRCUIT USING HIGH DENSITY PROBE POINTS 失效
标题翻译：生产和集成电路的测试中使用测试点高密度
公开(公告)号：EP0515577B1
公开(公告)日：1998-07-01
申请号：EP91908938.3
申请日：1991-02-14
申请人： LEEDY, Glenn J.
发明人： LEEDY, Glenn J.
IPC分类号： H05K3/30 , B44C1/22 , G01R1/04 , B05D5/12
CPC分类号： G11C29/006 , G01R1/06716 , G01R1/07307 , G01R1/07314 , G01R1/0735 , G01R31/2831 , G01R31/2863 , G01R31/287 , G01R31/2886 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G01R31/31912 , G03F7/70466 , G03F7/70658 , H01L22/22 , H01L2924/15192 , H01L2924/3011 , Y10T29/4913 , Y10T29/49155 , Y10T29/49764
摘要： Each transistor or logic unit on an integrated wafer (1) is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer syste. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than wich conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by specially fabricated flexible tester surface (10) made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points (15-1, 15-2) on one side of the test surface (10). The probe points (330) electrically contact the contacts (2-1, 2-2) on the wafer (1) under test by fluid pressure.

49. 发明公开

EP0845680A1 Making and testing an integrated circuit using high density probe points 失效
标题翻译： Fabrikation und Testen von integrierten Schaltungen mit Testpunkten hoher Dichte
公开(公告)号：EP0845680A1
公开(公告)日：1998-06-03
申请号：EP97122519.8
申请日：1991-02-14
申请人： LEEDY, Glenn J.
发明人： LEEDY, Glenn J.
IPC分类号： G01R31/316
CPC分类号： G11C29/006 , G01R1/06716 , G01R1/07307 , G01R1/07314 , G01R1/0735 , G01R31/2831 , G01R31/2863 , G01R31/287 , G01R31/2886 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G01R31/31912 , G03F7/70466 , G03F7/70658 , H01L22/22 , H01L2924/15192 , H01L2924/3011 , Y10T29/4913 , Y10T29/49155 , Y10T29/49764
摘要： Each transistor or logic unit on an integrated wafer (1) is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer syste. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than wich conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by specially fabricated flexible tester surface (10) made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points (15-1, 15-2) on one side of the test surface (10). The probe points (330) electrically contact the contacts (2-1, 2-2) on the wafer (1) under test by fluid pressure.
摘要翻译：在互连金属化之前测试集成晶片（1）上的每个晶体管或逻辑单元。通过CAD软件，修改了晶体管或逻辑单元布局网表，以替代有缺陷的冗余无缺陷逻辑单元。然后在CAD计算机系统的控制下布线和图案化互连金属化。因此，晶片中的每个管芯具有其自己的互连方案，尽管每个管芯在功能上是等效的，并且产量远高于在完成的电路级别的常规测试。单个晶体管或逻辑单元测试通过在几层柔性二氧化硅的一个实施例中制造的特殊制造的柔性测试仪表面（10）来实现，每个层包含通孔和导电迹线，导通数千个微观金属探针点（15-1， 15-2）在测试表面（10）的一侧。探针点（330）通过流体压力与待测晶片（1）上的触点（2-1,2-2）电接触。

50. 发明公开

EP0557079A3 Discretionary lithography for integrated circuits 失效
标题翻译：集成电路的分辨率图
公开(公告)号：EP0557079A3
公开(公告)日：1995-04-12
申请号：EP93301161.1
申请日：1993-02-17
申请人： DRI TECHNOLOGY CORPORATION
发明人： Leedy, Glenn J.
IPC分类号： G06F11/20 , H01L23/525 , H01L21/66
CPC分类号： G03F7/70466 , G11C29/006 , H01L22/22 , H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： Large scale integrated circuits are fabricated using redundant circuit elements to replace defective circuit elements by discretionary interconnect changes as determined by fine-grain testing of the integrated circuits after the logic units (such as individual transistors or logic gates) are fabricated and before they are electrically interconnected. The redundant circuit elements are then interconnected to non-defective circuit elements by one of two methods. In the first method a stepper-scanner apparatus modified to expose most of a resist layer defines the interconnect circuitry, but is shuttered-off over the discretionary interconnect changes. Then the discretionary interconnect changes are exposed by a conventional direct write on wafer pattern generation apparatus. In the second method, the interconnect patterning is accomplished by first fabricating a fixed custom mask defining the interconnect layer for a particular lot size (such as 100) of wafers. The fixed mask is fabricated after each wafer of the lot has been tested, and incorporates all the discretionary changes required to avoid interconnection to each defective circuit element in each of the wafers. The fixed custom mask is then used to expose the resist layer defining the interconnect circuitry for each of the 100 wafers.

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