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41. 发明公开

EP0745859A2 Configurable probe pads to facilitate parallel testing of integrated circuit devices 失效
标题翻译： Konfigurierbare Kontaktleiste zur bequemen parallellenPrüfungvon integrierten Schaltungen
公开(公告)号：EP0745859A2
公开(公告)日：1996-12-04
申请号：EP96302949.1
申请日：1996-04-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Brannigan, Michael Joseph , Lysinger, Mark Alan , McClure, David Charles
IPC分类号： G01R1/04
CPC分类号： G01R31/2884 , G01R31/2831 , G11C29/48
摘要： According to the present invention, parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by muitiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.
摘要翻译：根据本发明，集成电路器件的并行测试方便，因此并不需要将并联测试的集成电路器件设为“仅限端”器件。沿着集成电路器件的侧面而不是端部设置的侧焊盘通过多路复用电路电连接到沿着器件的端部设置的对应的可配置探针焊盘。在对器件进行并行测试时，可以对可配置的探头焊盘进行探测和测试时，对侧面焊盘进行有效测试。虽然在并行测试期间对可配置的探头焊盘进行了测试，但是侧面垫没有直接运行。在进行并行测试之后，侧面焊盘接合到器件封装，但是可配置的探针焊盘没有粘合到器件封装。

42. 发明公开

EP0735685A3 Programmable power reduction circuit for programmable logic device 失效
标题翻译：可编程逻辑器件的可编程功耗降低电路
公开(公告)号：EP0735685A3
公开(公告)日：1996-11-13
申请号：EP96109371.3
申请日：1991-05-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Steele, Randy C.
IPC分类号： H03K19/00 , H03K19/177
CPC分类号： H03K19/17748 , H03K19/0016 , H03K19/17704 , H03K19/1776 , H03K19/17784
摘要： According to the present invention, during programming of a programmable logic device, programming in formation corresponding to an input signal is loaded into a shift register. This input information is compared with programming information corresponding to a second, complementary input signal to determine if the two signals are used by the programmable logic device. If the two inputs are not used, a bit is stored in a memory cell indicating such nonuse. An input buffer is disabled when the bit in the memory cell indicates the complementary signals corresponding to that input buffer are not used.
摘要翻译：根据本发明，在可编程逻辑器件的编程期间，对应于输入信号的编程信息被加载到移位寄存器中。将该输入信息与对应于第二互补输入信号的编程信息进行比较，以确定两个信号是否被可编程逻辑器件使用。如果两个输入未被使用，则一位存储在存储单元中，指示这种不使用。当存储单元中的位指示没有使用对应于该输入缓冲器的互补信号时，禁止输入缓冲器。

43. 发明公开

EP0718881A3 Isolation by active transistors with grounded gates 失效
标题翻译：通过栅极接地的有源晶体管进行隔离
公开(公告)号：EP0718881A3
公开(公告)日：1996-10-16
申请号：EP95308542.0
申请日：1995-11-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Chan, Tsiu Chiu
IPC分类号： H01L21/765 , H01L27/118
CPC分类号： H01L21/76 , H01L21/761 , H01L21/765 , H01L27/11807
摘要： An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the substrate, by buried contact if desired, and can further be electrically connected to a source region formed within the active area. The polycrystalline silicon layer and substrate are connected to ground potential, thus preventing current flow between active areas.
摘要翻译：在P型半导体衬底上的有源区之间形成隔离栅结构。隔离结构包括其上形成P掺杂多晶硅层的厚栅极氧化物层。如果需要，多晶硅层通过掩埋接触电连接到衬底，并且可以进一步电连接到在有源区内形成的源极区。多晶硅层和衬底连接到地电位，从而防止有源区之间的电流流动。

44. 发明公开

EP0735687A2 Output driver with programmable drive characteristics 失效
标题翻译： Ausgangstreiber mit programmierbaren Treiberparametern
公开(公告)号：EP0735687A2
公开(公告)日：1996-10-02
申请号：EP96302174.6
申请日：1996-03-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David C.
IPC分类号： H03K19/0185
CPC分类号： H03K19/00361 , H03K19/018585
摘要： An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses, so that the output impedance of the voltage reference and regulator circuit may be selected. Slew rate control for output driver transistors is also provided, under the control of a bias circuit that generates a tracking reference voltage; the reference voltage may also be programmed by way of fuses or by control signals, so that the slew rate may also be selected.
摘要翻译：公开了用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。还公开了用于产生有限输出高电压的电压参考和调节器电路，并且基于电流镜。电流镜中的电流之和由偏置电流源控制，偏置电流源可以在操作周期内动态控制或通过熔断器编程，从而可以选择电压基准和调节器电路的输出阻抗。在产生跟踪参考电压的偏置电路的控制下，还提供输出驱动晶体管的转换速率控制; 参考电压也可以通过熔丝或控制信号进行编程，从而也可以选择转换速率。

45. 发明授权

EP0491523B1 A semiconductor memory with precharged redundancy multiplexing 失效
标题翻译：半导体存储器预充电冗余复用器
公开(公告)号：EP0491523B1
公开(公告)日：1996-09-11
申请号：EP91311569.7
申请日：1991-12-12
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles
IPC分类号： G06F11/20
CPC分类号： G11C29/84
摘要： An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array (12), and in which multiple input/output terminals are placed in communication with multiple columns in the sub-array in read and write cycles. The number of redundant columns per sub-array is less than the number of input(38)/output(20) terminals. A multiplexer connects the selected redundant column to a selected sense amplifier and write circuit for the input/output with which the replaced column was associated. The multiplexer includes pass gates connected to the bit lines of the redundant column, and fuses connected between each of the pass gates and each of the sense/write circuits selectable for the redundant (25) column. Those of the fuses which are not associated with the selected input/output are opened, and the fuses associated with the selected input/output are left intact. Precharge transistors are connected to the fuse sides of the pass gates, for precharging each of the floating nodes after the pass gates are turned off. This precharging negates the effect of any charge which may be trapped on the fuse side of the pass gates for those lines where the fuses are opened, so that the access time for the next cycle will not be degraded.

46. 发明公开

EP0730302A2 Vertical switched-emitter structure with improved lateral isolation 失效
标题翻译： Vertikale geschaltete-emittor Struktur mit verbesserter lateraler隔离
公开(公告)号：EP0730302A2
公开(公告)日：1996-09-04
申请号：EP96301273.7
申请日：1996-02-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Blanchard, Richard A.
IPC分类号： H01L27/07
CPC分类号： H01L29/7813 , H01L27/0605 , H01L27/0716 , H01L27/088 , H01L29/0878 , H01L29/1054 , H01L29/7302 , H01L29/7395 , H01L29/7397 , H01L29/7803 , Y10S148/126
摘要： A vertical switched-emitter device structure in which the body of a vertical-current-flow MOS device is formed in a P-type surface epi region, and dielectric isolation laterally separates the body from the surface contact to the buried P-type base region.
摘要翻译：垂直开关 - 发射极器件结构，其中垂直电流流动MOS器件的主体形成在P型表面epi区域中，并且绝缘隔离将主体与表面接触侧向分离成掩埋P型基极区域。

47. 发明公开

EP0720152A3 AC input stage with reduced transient time for use in multiplexing transducers that require a switched DC bias 失效
标题翻译：这需要具有用于多路复用器切换的DC偏置电流减小的沉降时间的AC电压输入级
公开(公告)号：EP0720152A3
公开(公告)日：1996-08-28
申请号：EP95309394.5
申请日：1995-12-22
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Cameron, Scott W. , Alegre de la Soujeole, Axel
IPC分类号： G11B5/02 , H03F1/30
CPC分类号： G11B5/02 , G11B2005/0016 , G11B2005/0018 , H03F3/72 , H03F2200/372
摘要： The present application discloses an innovative improved circuit, in which the long transient at write-to-read transitions is avoided by using a shorting switch (M1) to short the inputs of the first amplifier stage (A1) together when the read amplifier is activated. This speeds up write-to-read transition. Moreover, since read mode can now be entered more quickly after a power-down condition, this circuit also permits the use of other power-saving tricks to idle the read amplifier momentarily.

48. 发明公开

EP0720150A3 Symmetrical resistive transducer biasing circuit and methods 失效
标题翻译： Symmetrischer ohmischerÜbstrager，Vorstromschaltung und Verfahren dazu
公开(公告)号：EP0720150A3
公开(公告)日：1996-08-28
申请号：EP95309392.9
申请日：1995-12-22
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Cameron, Scott W. , Alegre de la Soujeole, Axel
IPC分类号： G11B5/02 , G11B5/03 , H03F3/45
CPC分类号： H03F3/45479 , G11B5/02 , G11B5/40 , G11B19/04 , G11B2005/0018 , H03F2200/372
摘要： An innovative disk drive system which provides a regulated bias current to a magnetoresistive read head, and controls the voltage of the magnetoresistive read head terminals so that the CENTER of the resistor is at ground. This halves the peak magnitude of the head-to-disk voltage.
摘要翻译：一种创新的磁盘驱动器系统，其向磁阻读取头提供稳定的偏置电流，并且控制磁阻读头终端的电压，使得电阻器的CENTER处于接地状态。这将磁头电压峰值幅度减半。

49. 发明公开

EP0691729A3 Charge pump circuit with feedback control 失效
标题翻译：电荷泵电路与反馈控制
公开(公告)号：EP0691729A3
公开(公告)日：1996-08-14
申请号：EP95304442.7
申请日：1995-06-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Canclini, Athos
IPC分类号： H02M3/07
CPC分类号： H02M3/073
摘要： A charge pump circuit with negative current feedback is dislcosed. The charge pump circuit consists of charge pump stages, switch circuits in between the stages, and a feedback loop to control the conductivity of the switch circuit. The conductivity of the switch circuits is controlled by modulating the bias current of the switch circuit which modulates its conductivity. By using the feedback loop to control the conductivity, the output voltage of the charge pump circuit can be regulated.

50. 发明公开

EP0720152A2 AC input stage with reduced transient time for use in multiplexing transducers that require a switched DC bias 失效
标题翻译：这需要具有用于多路复用器切换的DC偏置电流减小的沉降时间的AC电压输入级
公开(公告)号：EP0720152A2
公开(公告)日：1996-07-03
申请号：EP95309394.5
申请日：1995-12-22
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Cameron, Scott W. , Alegre de la Soujeole, Axel
IPC分类号： G11B5/02 , H03F1/30
CPC分类号： G11B5/02 , G11B2005/0016 , G11B2005/0018 , H03F3/72 , H03F2200/372
摘要： The present application discloses an innovative improved circuit, in which the long transient at write-to-read transitions is avoided by using a shorting switch (M1) to short the inputs of the first amplifier stage (A1) together when the read amplifier is activated. This speeds up write-to-read transition. Moreover, since read mode can now be entered more quickly after a power-down condition, this circuit also permits the use of other power-saving tricks to idle the read amplifier momentarily.
摘要翻译：其中长瞬态在写阅读的转变是通过使用短路开关（M1），以短的第一放大器级的输入端（A1）一起当读放大器被激活避免本申请圆盘缺乏创新改进的电路，这加快了写阅读的转变。更结束了，因为读模式，现在可以更迅速地断电状态进入后，该电路从而允许使用其他省电技巧来暂时闲置的读放大器。

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