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31. 发明公开

EP3008751A4 INTEGRATED SILICON AND III-N SEMICONDUCTOR DEVICE 有权
标题翻译： IN III-N-HALBLEITERBAUELEUM IN INIGIGERERTES SILIIUM UND III-N-HALBLEITERBAUELEMENT
公开(公告)号：EP3008751A4
公开(公告)日：2017-03-15
申请号：EP14791900
申请日：2014-05-05
申请人： TEXAS INSTRUMENTS INC
发明人： TIPIRNENI NAVEEN , PENDHARKAR SAMEER , WISE RICK L
IPC分类号： H01L21/8258 , H01L21/18
CPC分类号： H01L21/187 , H01L21/76254 , H01L21/8258

32. 发明公开

EP2878007A4 SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION 审中-公开
标题翻译：自对准外延3D结构为MOS装置生产
公开(公告)号：EP2878007A4
公开(公告)日：2016-03-02
申请号：EP13822511
申请日：2013-06-12
申请人： INTEL CORP
发明人： GLASS GLENN A , AUBERTINE DANIEL B , MURTHY ANAND S , THAREJA GAURAV , GHANI TAHIR
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L29/1054
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

33. 发明公开

EP2795675A4 HYBRID INTEGRATION OF GROUP III-V SEMICONDUCTOR DEVICES ON SILICON 审中-公开
标题翻译：硅的III-V族半导体元件的混合集成
公开(公告)号：EP2795675A4
公开(公告)日：2015-11-25
申请号：EP11878060
申请日：2011-12-20
申请人： INTEL CORP
发明人： HECK JOHN , BAR HANAN , FESHALI AVI , FELDESH RAN
IPC分类号： H01L27/14 , G02B6/12
CPC分类号： G02B6/1225 , G02B6/12004 , G02B6/13 , G02B2006/12061 , H01L21/28575 , H01L21/8252 , H01L21/8258 , H01L21/84 , H01L27/1203 , H01L29/205

34. 发明公开

EP2805352A4 VERTICAL INTEGRATION OF CMOS ELECTRONICS WITH PHOTONIC DEVICES 有权转让
标题翻译：与光子器件CMOS电子垂直整合
公开(公告)号：EP2805352A4
公开(公告)日：2015-09-09
申请号：EP13738701
申请日：2013-01-18
申请人： SKORPIOS TECHNOLOGIES INC
发明人： DALLESASSE JOHN , KRASULICK STEPHEN B , CREAZZO TIMOTHY , MARCHENA ELTON
IPC分类号： H01L27/12 , H01L21/8258 , H01L21/84 , H01L27/06
CPC分类号： H01L27/14689 , H01L21/76254 , H01L21/8221 , H01L21/8258 , H01L21/84 , H01L27/0688 , H01L27/12 , H01L27/14625 , H01L27/14634 , H01L27/14643 , H01L27/14687 , H01L27/15
摘要： A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.

35. 发明公开

EP2805352A1 VERTICAL INTEGRATION OF CMOS ELECTRONICS WITH PHOTONIC DEVICES 有权转让
标题翻译： VERTIKALE INTEGRATION VON CMOS-ELEKTRONIK MIT PHOTONISCHEN BAUELEMENTEN
公开(公告)号：EP2805352A1
公开(公告)日：2014-11-26
申请号：EP13738701.5
申请日：2013-01-18
申请人： Skorpios Technologies, Inc.
发明人： DALLESASSE, John , KRASULICK, Stephen B. , CREAZZO, Timothy , MARCHENA, Elton
IPC分类号： H01L27/14 , H01L27/12
CPC分类号： H01L27/14689 , H01L21/76254 , H01L21/8221 , H01L21/8258 , H01L21/84 , H01L27/0688 , H01L27/12 , H01L27/14625 , H01L27/14634 , H01L27/14643 , H01L27/14687 , H01L27/15
摘要： A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.
摘要翻译：制造复合半导体结构的方法包括提供包括多个硅基器件的SOI衬底，提供包括多个光子器件的化合物半导体衬底，以及切割化合物半导体衬底以提供多个光子管芯。每个管芯包括多个光子器件中的一个或多个。该方法还包括提供具有基底层和包括多个CMOS器件的器件层的组装衬底，将多个光子管芯安装在组装衬底的预定部分上，以及对准SOI衬底和组件衬底。该方法还包括将SOI衬底和组件衬底接合以形成复合衬底结构，并从组合衬底结构去除组装衬底的至少基底层。

36. 发明公开

EP2494594A4 SEMICONDUCTOR DEVICE 有权转让
公开(公告)号：EP2494594A4
公开(公告)日：2014-05-28
申请号：EP10826485
申请日：2010-09-29
申请人： SEMICONDUCTOR ENERGY LAB
发明人： YAMAZAKI SHUNPEI , IMAI KEITARO , KOYAMA JUN
IPC分类号： H01L21/8234 , G11C11/404 , G11C11/405 , G11C16/02 , H01L21/8238 , H01L21/8258 , H01L27/00 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/115 , H01L27/12 , H01L29/786 , H03K19/20
CPC分类号： H01L27/10802 , G11C11/404 , G11C11/405 , G11C16/02 , H01L21/8258 , H01L27/0688 , H01L27/088 , H01L27/0922 , H01L27/105 , H01L27/1156 , H01L27/12 , H01L27/1225 , H01L29/7869
摘要： The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

37. 发明公开

EP2595175A3 Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication 审中-公开
公开(公告)号：EP2595175A3
公开(公告)日：2013-07-17
申请号：EP13155283.8
申请日：2006-05-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Cheng, Zhiyuan , Currie, Matthew T. , Lochtefeld, Anthony J. , Fiorenza, James , Langdo, Thomas A. , Braithwaite, Glyn
IPC分类号： H01L21/20 , H01L21/02 , H01L29/66 , H01L21/762 , H01L29/78
CPC分类号： H01L21/02647 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/02639 , H01L21/7624 , H01L21/8258 , H01L29/66795 , H01L29/785
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

38. 发明公开

EP2333822A2 High voltage durability III-nitride semiconductor device 审中-公开
标题翻译：高耐压III族氮化物半导体器件
公开(公告)号：EP2333822A2
公开(公告)日：2011-06-15
申请号：EP10015287.5
申请日：2010-12-03
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H01L21/335 , H01L29/04 , H01L29/20 , H01L29/778
CPC分类号： H01L29/778 , H01L21/8258 , H01L29/045 , H01L29/2003 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： A high voltage durability III-nitride semiconductor device comprises a support substrate (10) including a first silicon body (14), an insulator body (18) over the first silicon body (14), and a second silicon body (16) over the insulator body (18). The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body (12) characterized by a majority charge carrier conductivity type, formed over the second silicon body (16). The second silicon body (16) has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate (10) including a silicon layer (14), an insulator layer (18) over the silicon layer (14), and a P type conductivity silicon layer (16) over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body (12) formed over the P type conductivity silicon layer (16), the III-nitride semiconductor body (12) forming a heterojunction of the HEMT.
摘要翻译：一种高电压耐久性III族氮化物半导体器件，包括：支撑衬底（10），其包括第一硅本体（14），在第一硅本体（14）上的绝缘体本体（18）以及第二硅本体绝缘体（18）。高电压耐久性III族氮化物半导体器件还包括形成在第二硅本体（16）之上的以多数电荷载流子传导型为特征的III族氮化物半导体本体（12）。第二硅体（16）具有与多数电荷载流子导电类型相反的导电类型。在一个实施例中，高电压耐久性III族氮化物半导体器件是高电子迁移率晶体管（HEMT），其包括包含<100>硅层（14）的支撑衬底（10），<100 >硅层（14）以及绝缘层上的P型导电<111>硅层（16）。高电压耐久性HEMT还包括在P型导电<111>硅层（16）上形成的III族氮化物半导体主体（12），III族氮化物半导体主体（12）形成HEMT的异质结。

39. 发明公开

EP2296169A1 METHOD FOR MANUFACTURING NITROGEN COMPOUND SEMICONDUCTOR SUBSTRATE, NITROGEN COMPOUND SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SINGLE CRYSTAL SIC SUBSTRATE, AND SINGLE CRYSTAL SIC SUBSTRATE 有权
标题翻译： METHOD FOR PRODUCTION氮化合物半导体基板，氮化合物半导体基板，制造SiC单晶衬底和EINKRISTALLIGES SiC衬底的方法的
公开(公告)号：EP2296169A1
公开(公告)日：2011-03-16
申请号：EP09762563.6
申请日：2009-06-09
申请人： Air Water Inc. , Osaka Prefecture University
发明人： KAWAMURA, Keisuke , IZUMI, Katsutoshi , ASAMURA, Hidetoshi , YOKOYAMA, Takashi
IPC分类号： H01L21/02 , H01L21/20 , H01L21/205 , H01L21/76 , H01L27/12
CPC分类号： H01L21/8258 , C30B25/02 , C30B29/36 , C30B29/403 , H01L21/02381 , H01L21/02447 , H01L21/0254 , H01L21/02614 , H01L21/8213
摘要： In order to provide a method for manufacturing a nitrogen compound semiconductor substrate that can obtain a nitrogen compound semiconductor layer with good crystallinity, there are performed, preparing an Si substrate 1 having a surface Si layer 3 of a predetermined thickness and an embedded insulating layer 4, leaving, when the Si substrate 1 is heated in a carbon-series gas atmosphere to convert the surface Si layer 3 into a single crystal SiC layer 6, the Si layer in the vicinity of an interface 8 with the embedded insulating layer 4 as a residual Si layer 5, and further epitaxially growing a nitrogen compound semiconductor layer 15 on surface single crystal SiC.
In order to provide a method for manufacturing a single crystal SiC substrate that can obtain an SiC layer with good crystallinity, an Si substrate 1 having a surface Si layer 3 of a predetermined thickness and an embedded insulating layer 4 is prepared, and when the Si substrate 1 is heated in a carbon-series gas atmosphere to convert the surface Si layer 3 into a single crystal SiC layer 6, when converting the surface Si layer 3 into a single crystal SiC layer 6, the Si layer in the vicinity of an interface 8 with the embedded insulating layer 4 is left as a residual Si layer 5.

40. 发明公开

EP2255387A1 INTEGRATED NITRIDE AND SILICON CARBIDE-BASED DEVICES AND METHODS OF FABRICATING INTEGRATED NITRIDE-BASED DEVICES 有权
标题翻译：集成器件的氮化物和碳化硅AND METHOD FOR PRODUCING集成器件的氮化物
公开(公告)号：EP2255387A1
公开(公告)日：2010-12-01
申请号：EP09722679.9
申请日：2009-02-09
申请人： Cree, Inc.
发明人： SHEPPARD, Scott T.
IPC分类号： H01L21/8252 , H01L21/8258 , H01L27/06
CPC分类号： H01L27/0605 , H01L21/8213 , H01L21/8252 , H01L21/8258 , H01L27/20 , H01L29/2003 , H01L29/7787 , H03H3/08 , H03H9/02228 , H03H9/02574 , H03H9/02976 , H03H9/0542
摘要： Monolithic electronic devices including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a first doping concentration greater than a doping concentration of the common nitride epitaxial layer. A second type of nitride device, different from the first type of nitride device, including a second at least one implanted n-type region is provided on the common nitride epitaxial layer. The second at least one implanted n-type region is different from the first at least one implanted n-type region and has a second doping concentration that is greater than the doping concentration of the common nitride epitaxial layer. A first plurality of electrical contacts are provided on the first at least one implanted n-type region. The first plurality of contacts define a first electronic device of the first type of nitride device. A second plurality of electrical contacts are provided on the second at least one n-type implanted region. The second plurality of contacts define a second electronic device of the second type of electronic device. Corresponding methods are also disclosed.

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