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31. 发明公开

EP0961978A1 PC CHIPSET INTERCONNECTION BUS 失效
标题翻译： PC CHIPANORDNUNGVERBINDUNGSBUS
公开(公告)号：EP0961978A1
公开(公告)日：1999-12-08
申请号：EP98908574.0
申请日：1998-02-14
申请人： Advanced Micro Devices, Inc.
发明人： GULICK, Dale, E.
IPC分类号： G06F13
CPC分类号： G06F13/423
摘要： A bus connects a first and second integrated circuit. The bus includes a frame sync line which indicates the beginning of a frame when asserted, each frame containing a predetermined number time slots. A data out line provides data from the first to the second integrated circuit. The data represents the state of signals to be provided on output terminals of the second integrated circuit. Each of the data bits is assigned one of the time slots in the frame. A data in line provides a predetermined number of second data bits from the second to the first integrated circuit during each frame. Each of the second data bits is assigned one of the time slots and includes data including data bits indicating the state of input terminals of the second integrated circuit. A clock signal defines the time slots within the frame. The bus operates to provide frames substantially continuously between the first and second integrated circuit while the first and second integrated circuits.

32. 发明公开

EP0925667A2 LOW POWER SERIAL PROTOCOL TRANSLATOR FOR USE IN MULTI-CIRCUIT BOARD ELECTRONIC SYSTEMS 失效
标题翻译：具有低功耗串行连接的电子系统与更多的电路卡协议转换器
公开(公告)号：EP0925667A2
公开(公告)日：1999-06-30
申请号：EP97939894.0
申请日：1997-09-09
申请人： SIERRA WIRELESS, INC.
发明人： DUTKIEWICZ, Marek , LI, Henry
IPC分类号： G06F13 , H04L12
CPC分类号： H04L12/40 , G06F13/423 , Y02D10/14 , Y02D10/151
摘要： A low power reduced size serial device protocol translator including a slave controller and detection circuit for detecting start and stop conditions on serial data (SDA) and serial clock (SCL) lines in a serial communication system is described. The start and stop condition detector includes two flip-flops; one for providing a signal that indicates when a start condition has occurred on the SDA and SCL lines and another for indicating when a stop condition has occurred. Each of the flip-flops have their data inputs coupled to a high logic level and their enable input coupled to the serial clock line. The first flip-flop for indicating the start condition has its clock input coupled to the inverse of the serial data signal and the second flip-flop for indicating the stop condition has its clock input directly coupled to the serial data signal. As a result, the first and second flip-flops are only enabled and clocked when either a start or stop condition is occurring, resulting in an extremely low power slave controller detection system. The translator of the present invention translates serial signals between slave and master devices having different protocol types. The translator utilizes sub-protocol signals including length information corresponding to the number of data bits being transmitted to the slave device. The translator uses the length information to gate the serial data from the master device to the slave device. The translator allows for reduction of physical interconnections in a master/slave system in which a master devices resides on a first printed circuit board (PCB) and communicates with slave devices on a second PCB having more than one type of serial communication protocol. In this case, the translator resides on the same PCB as the slave devices thus requiring that only the serial buses corresponding to the master device protocol type be physically coupled across the two PCB's interconnection interface.

33. 发明公开

EP0811197A1 SYSTEM MANAGEMENT SHADOW PORT 失效
标题翻译：附加门系统管理
公开(公告)号：EP0811197A1
公开(公告)日：1997-12-10
申请号：EP95911910.0
申请日：1995-02-24
申请人： INTEL CORPORATION
发明人： DATTA, Sham , JOSHI, Jayesh , KARDACH, James, P.
IPC分类号： G06F1 , G06F13
CPC分类号： G06F1/3215 , G06F13/423
摘要： A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers (22) samples information from a system bus (16). Such information is obtained by a register accessing the plurality of system management shadow registers (22) through a common shadow port.

34. 发明公开

EP0769748A1 Cellule intégrable DDC dédiée à un microprocesseur 有权转让
标题翻译： Mikroprozessorgewidmete integrierbare DDC-Zelle
公开(公告)号：EP0769748A1
公开(公告)日：1997-04-23
申请号：EP96470020.7
申请日：1996-09-27
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Marsanne, Sébastien , Maquin, Francis
IPC分类号： G06F13/42
CPC分类号： G06F13/423
摘要： Cellule (12), d'un circuit intégré, dédiée à un microprocesseur (7) comportant:

une entrée/sortie de données reliée à un réseau de communication fonctionnant selon au moins deux protocoles différents dits DDC1 et I2C,
un circuit de contrôle muni d'un séquenceur, le circuit de contrôle étant géré par le séquenceur, le circuit de contrôle communiquant avec un bus de contrôle de ce microprocesseur (7), le circuit de contrôle communiquant avec l'entrée/sortie de données;
caractérisée en ce qu'elle comporte un circuit logique pour forcer l'état du séquenceur en fonction d'une information relative à la nature du protocole utilisé.
摘要翻译：专用于微处理器（7）的接口单元（12）具有连接到微处理器数据总线（9）的第一输入 - 输出电路（15）。第二输入输出电路（16）连接到在两种协议（DDC1，I2C）上工作的通信网络。数据处理电路（13）连接在两个输入输出电路（15,16）之间，并且该设备由包含定序器（18）的控制电路（14）引导。控制电路与微处理器（7）的控制总线通信，逻辑电路（203）根据所使用的协议激活定序器（18）。

35. 发明公开

EP0679307A1 DELAY LINE SEPARATOR FOR DATA BUS 失效
标题翻译：用于数据总线的延迟线分离器
公开(公告)号：EP0679307A1
公开(公告)日：1995-11-02
申请号：EP94909468.0
申请日：1994-01-12
申请人： APPLE COMPUTER, INC.
发明人： VAN BRUNT, Roger , OPRESCU, Florin
IPC分类号： G06F13 , H04L7
CPC分类号： H04L7/0066 , G06F13/423
摘要： The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as desired, to generate additional clock signals delayed by 5- or 10-nanosecond intervals.
摘要翻译：尽管存在明显的占空比失真，延迟线分离器从通过串行数据总线接收的组合数据/时钟编码信号中提取时钟信号。这种失真会影响接收数据包内符号的宽度，但不会影响接收到的脉冲串内连续上升沿之间的定时。为了从失真信号中提取时钟信号，分离器利用一个预滤波器电路，该电路产生与接收信号中每个上升沿同步的20纳秒脉冲。 20纳秒脉冲串沿着具有12个延迟元件的延迟线传输。电路连接到延迟线内的每个其他延迟元件，以产生与脉冲序列的每个上升沿同步的10纳秒脉冲。来自电路的输出使用或门组合以产生10纳秒时钟信号。预滤波器产生20纳秒脉冲而不是10纳秒脉冲，以确保脉冲成功传播延迟线的整个长度，尽管在每个延迟元件内存在显着的色散。根据需要，额外的电路被分接到延迟元件中，以产生延迟5或10纳秒间隔的附加时钟信号。

36. 发明公开

EP0549334A3 A data input and output control device and a one-chip microcomputer integrating the same 失效
标题翻译：一个数据输入和输出控制装置和一个一体化微型计算机集成
公开(公告)号：EP0549334A3
公开(公告)日：1994-10-26
申请号：EP92311725.3
申请日：1992-12-22
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Okamoto, Minoru , Sakakibara, Mikio
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a data input/output control device integrating a one-chip microcomputer together with a data transfer device and a processor, the data transfer device being constructed to transmit to and receive from an external apparatus serial data and the processor processing data inputted to the data transfer device and transmitting the processed data to the data transfer device to be further transmitted to the external apparatus, the date input/output control device characterized in that a clock of the data input/output control device for an operation thereof is a transfer clock utilized by the external apparatus and the transfer clock is slower than a clock for the processor. The data input/output control device comprises a controller for controlling the data input and the data output of the data transfer device, a flag holding unit for holding a flag which shows if the data have been inputted to the data transfer device by the processor or the external apparatus, a first synchronization circuit for synchronizing an output from the flag holding unit with the transfer clock, the output being sent to the controller, and a second synchronization circuit for synchronizing the output from the flag holding unit with the clock for the processor.
摘要翻译：本发明提供一种数据输入/输出控制装置，其将单片微计算机与数据传送装置和处理器一体化，所述数据传送装置被构造成向外部设备发送和接收串行数据和输入的处理器处理数据所述数据输入/输出控制装置的特征在于，所述数据输入/输出控制装置的操作时钟为数据传送装置，所述数据输入/输出控制装置的时钟为由外部设备和传输时钟使用的传输时钟比处理器的时钟慢。数据输入/输出控制装置包括用于控制数据输入和数据传输装置的数据输出的控制器，标记保持单元，用于保持标志，该标志显示数据是否已被处理器输入到数据传送装置;或者外部设备，用于将来自标志保持单元的输出与传送时钟同步的第一同步电路，输出被发送到控制器，以及第二同步电路，用于使来自标志保持单元的输出与处理器的时钟同步。

37. 发明公开

EP0549334A2 A data input and output control device and a one-chip microcomputer integrating the same 失效
标题翻译：控制装置，用于数据输入/输出，并且这些腿部保持单芯片微型计算机。
公开(公告)号：EP0549334A2
公开(公告)日：1993-06-30
申请号：EP92311725.3
申请日：1992-12-22
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Okamoto, Minoru , Sakakibara, Mikio
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a data input/output control device integrating a one-chip microcomputer together with a data transfer device and a processor, the data transfer device being constructed to transmit to and receive from an external apparatus serial data and the processor processing data inputted to the data transfer device and transmitting the processed data to the data transfer device to be further transmitted to the external apparatus, the date input/output control device characterized in that a clock of the data input/output control device for an operation thereof is a transfer clock utilized by the external apparatus and the transfer clock is slower than a clock for the processor.
The data input/output control device comprises a controller for controlling the data input and the data output of the data transfer device, a flag holding unit for holding a flag which shows if the data have been inputted to the data transfer device by the processor or the external apparatus, a first synchronization circuit for synchronizing an output from the flag holding unit with the transfer clock, the output being sent to the controller, and a second synchronization circuit for synchronizing the output from the flag holding unit with the clock for the processor.
摘要翻译：本发明提供一种具有数据传送装置和一个处理器INTEGRA婷数据输入/输出控制装置的单片微型计算机一起，所述数据传送装置被构造以发送到并从在输入的外部设备的串行数据，并且所述处理器处理数据接收于数据传送设备和所述处理后的数据发送到所述数据传输装置被进一步反式mitted到外部设备，在其特点日期输入/输出控制装置所做的数据输入/输出控制装置的时钟，用于在操作上是由外部设备和传送时钟可利用的传送时钟比用于所述处理器的时钟速度较慢。数据输入/输出控制装置包括一个控制器，用于控制数据输入和数据输出的数据传送装置的，用于保持一个标志，示出了如果数据已经由处理器或输入到数据传送装置中的标志保持部所述外部装置，用于从所述标志保持部同步，以输出与传输时钟的第一同步电路中，输出被发送到控制器，并用于与所述时钟同步从所述标志保持部的输出为所述处理器的第二同步电路，

38. 发明公开

EP0462622A3 Microprocessor capable of ensuring flexible recovery time for I/O device 失效
标题翻译：确保I / O设备灵活恢复时间的微处理器
公开(公告)号：EP0462622A3
公开(公告)日：1992-12-23
申请号：EP91110264.8
申请日：1991-06-21
申请人： NEC CORPORATION
发明人： Tsubota, Masashi, c/o NEC Corporation
IPC分类号： G06F13/42
CPC分类号： G06F13/423
摘要： A microprocessor which has bus cycles of a memory access operation, an I/O access operation, and an idle state, comprises a register for storing the number of the idle states to be inserted when first and second I/O accesses are consecutively executed, and a counter circuit for counting a clock when the first I/O access has been executed. A resetting circuit receives a signal indicating that the last access is the I/O access and resets the counter circuit when the first I/O access has been executed, and A comparator compares an output of the register with an output of the counter circuit for generating a recovery end signal when coincidence is detected. A timing generator generates state signals to the effect that the second I/O access is not executed until the recovery end signal is generated.

39. 发明公开

EP0417878A3 Interface control system 失效
标题翻译：接口控制系统
公开(公告)号：EP0417878A3
公开(公告)日：1992-04-29
申请号：EP90300471.1
申请日：1990-01-17
申请人： ACER INCORPORATED
发明人： Lan, Ray-Yuan
IPC分类号： G06F13/42 , G06F1/08
CPC分类号： G06F13/423 , G06F1/08
摘要： The interface control system of this invention renders a high speed CPU compatible with low speed expansion devices such as expansion interfaces. The system causes the CPU clock signal to be in phase with the interface clock signal at the end of the last cycle of an interface cycle. At the end of the interface cycle, the system selects between a positive high speed and a negative high speed clock to be the CPU clock signal applied to the CPU.

40. 发明授权

EP0175564B1 Data transfer system 有权转让
标题翻译：数据传输系统
公开(公告)号：EP0175564B1
公开(公告)日：1991-11-27
申请号：EP85306584.5
申请日：1985-09-17
申请人： AMT(HOLDINGS) LIMITED
发明人： Humpleman, Richard James
IPC分类号： G06F13/42
CPC分类号： G06F13/423

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