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32. 发明公开

EP0735452A3 Current-limit circuit 失效
标题翻译：限流电路
公开(公告)号：EP0735452A3
公开(公告)日：1997-02-05
申请号：EP96302063.1
申请日：1996-03-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Edwards, William Ernest
IPC分类号： G05F1/62 , G05F3/26
CPC分类号： G05F3/16 , G05F1/575 , G05F3/267
摘要： A current limiting circuit (50) used with voltage regulators or other similar circuits is disclosed. The current limiting circuit uses two transistors (60,68), configured as a differential pair, combined with a fixed current source (62) to limit the current available to a pass transistor (80) of the voltage regulator.

33. 发明公开

EP0753860A2 A semiconductor memory with a clocked access code for test mode entry 失效
标题翻译： Halbleiterspeicher mit einem Sequenz-getakteten Zugriffscode zum Eintritt in denPrüfmodus
公开(公告)号：EP0753860A2
公开(公告)日：1997-01-15
申请号：EP96113905.2
申请日：1991-08-12
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Slemmer, William Carl
IPC分类号： G11C29/00 , G01R31/318
CPC分类号： G11C29/46
摘要： An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgement of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.
摘要翻译：公开了具有正常操作模式和特殊操作模式（诸如特殊测试模式）的集成电路。特殊测试模式通过一系列信号启用，例如终端的过电压偏移，而不是单个这样的偏移，使得不经意地进入特殊测试模式的可能性较小，例如由于噪声或功率降低和启动设备。用于启用测试模式的电路包括一系列D型触发器，每个D型触发器在检测到过电压状态以及在另一个端子处施加的特定逻辑电平时被计时; 可以为多种特殊测试模式提供多个触发器系列。附加功能包括提供上电复位电路，该电路在器件上电期间锁定进入测试模式。进入测试模式的确认通过在器件未使能时在输出端子处呈现低阻抗来提供; 设备的芯片使能使设备退出测试模式。一旦进入测试模式，器件的输出使能端可提供芯片使能功能。

34. 发明授权

EP0420388B1 Test latch circuit 失效
标题翻译：测试闩锁电路
公开(公告)号：EP0420388B1
公开(公告)日：1997-01-08
申请号：EP90307156.1
申请日：1990-06-29
申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)
发明人： Doyle, Bruce Andrew
IPC分类号： G06F11/26
CPC分类号： G11C29/24 , G01R31/318516 , G11C29/52

35. 发明公开

EP0748048A1 Low power, low voltage level shifter 失效
标题翻译： Pegelelsfürkleine Speisespannungen mit geringem Verbrauch
公开(公告)号：EP0748048A1
公开(公告)日：1996-12-11
申请号：EP96303324.6
申请日：1996-05-13
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Yin, Rong
IPC分类号： H03K19/017
CPC分类号： H03K19/01707 , H03K19/0013
摘要： A low power, low voltage level shifter is provided. The voltage level shifter includes a first switching circuit, and a second switching circuit. The first switching circuit has a first input terminal for receiving a first oscillating signal, and based on the first oscillating signal, switches the output of the first switching circuit between a first voltage level and a second voltage level. The second switching circuit has a second input terminal connected to the output terminal of the first switching circuit. The second switching circuit also has a third input terminal for receiving a second oscillating signal which is out of phase with the first oscillating signal. Based on the input signals received, the second switching circuit generates an output signal that switches between a third voltage level and a fourth voltage level at a selected rate and frequency.
摘要翻译：提供了低功率，低电压电平转换器。电压电平移位器包括第一开关电路和第二开关电路。第一开关电路具有用于接收第一振荡信号的第一输入端，并且基于第一振荡信号，在第一电压电平和第二电压电平之间切换第一开关电路的输出。第二开关电路具有连接到第一开关电路的输出端的第二输入端。第二开关电路还具有用于接收与第一振荡信号异相的第二振荡信号的第三输入端。基于所接收的输入信号，第二开关电路产生以所选择的速率和频率在第三电压电平和第四电压电平之间切换的输出信号。

36. 发明公开

EP0745923A2 Voltage regulator with load pole stabilization 失效
标题翻译：负载极稳定的电压调节器
公开(公告)号：EP0745923A2
公开(公告)日：1996-12-04
申请号：EP96303017.6
申请日：1996-04-30
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Edwards, William Ernest
IPC分类号： G05F3/26
CPC分类号： G05F3/267
摘要： A voltage regulator with load pole stabilization is disclosed. The voltage regulator consists of an output stage, a comparator stage, and an active load. The active load draws current from the output of the voltage regulator inversely proportional to the current demand on the voltage regulator. When the output current demand is large, the active load draws relatively low current. When the output current demand is large, the active load draws a relatively large amount of current. Consequently, the disclosed voltage regulator has high stability without consuming excess power.
摘要翻译：公开了一种具有负载极稳定性的电压调节器。电压调节器由一个输出级，一个比较器级和一个有源负载组成。有功负载从电压调节器的输出端汲取电流，与电压调节器的电流需求成反比。当输出电流需求较大时，有功负载吸收较低的电流。当输出电流需求较大时，有功负载吸收相对较大的电流。因此，所公开的电压调节器具有高的稳定性而不消耗过多的功率

37. 发明公开

EP0745495A2 Circuit for driving the motor of a temperature blend door 失效
标题翻译： Schaltung zum Ansteuern eines Motors einer Temperaturregelklappe
公开(公告)号：EP0745495A2
公开(公告)日：1996-12-04
申请号：EP96302948.3
申请日：1996-04-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Swanson, David Frank
IPC分类号： B60H1/00
CPC分类号： H03K17/666 , B60H1/00857 , H02P7/288 , Y02T10/88
摘要： A circuit for driving a motor used to control the HVAC blend door in an automobile is disclosed. The circuit includes an amplifier circuit, a motor, and a three state driver circuit. The driver circuit includes three NPN bipolar transistors and two PNP bipolar transistors configured such that the output of the three state driver circuit is turned off if the input is at a intermediate voltage. The output of the three state driver circuit is at a high voltage if the input is at a low voltage. Conversely, the output of the three state driver circuit is at a low voltage when the input is at a high voltage.
摘要翻译：公开了一种用于驱动用于控制汽车中的HVAC混合门的马达的电路。该电路包括放大器电路，电动机和三态驱动器电路。驱动器电路包括三个NPN双极晶体管和两个PNP双极晶体管，其被配置为使得如果输入处于中间电压，则三态驱动电路的输出被截止。如果输入为低电压，则三态驱动电路的输出处于高电压。相反，当输入处于高电压时，三态驱动电路的输出处于低电压。

38. 发明公开

EP0632492A3 Method of forming self-aligned LDD structures and low resistance contacts in thin film transistor technology devices 失效
标题翻译：形成自对准的LDD结构和低的欧姆接触的薄膜晶体管技术的安排的方法。
公开(公告)号：EP0632492A3
公开(公告)日：1996-11-20
申请号：EP94304642.5
申请日：1994-06-27
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Sundaresan, Ravishankar
IPC分类号： H01L21/336 , H01L21/283 , H01L29/786 , H01L27/11 , H01L21/8244
CPC分类号： H01L29/66765 , H01L21/76889 , H01L27/11 , H01L27/1108 , H01L29/458 , H01L29/78621
摘要： A prior art thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi 2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists. The procedure to form low resistance contacts is extended to achieve a low leakage polysilicon TFT device. One or more LDD regions are formed to reduce the amount of leakage current of such transistor devices in an "OFF" state. The source/drain region(s) of the device are implanted with a first dopant type followed by an etch which forms spacers above the source/drain regions. Then, the source/drain regions are implanted with a second dopant type so that LDD regions are formed beneath the spacers. The electric field at the gate and source/drain boundaries of the device is spread over the entire LDD region, resulting in a lower peak electric field and hence less device leakage current.
摘要翻译：具有第一和不同导电型的第二多晶硅层（P和N）的现有技术的薄膜晶体管结构在所得到的P-N结的高电阻接触。如钴或钼中的特定区域，即P-N结的接触：该接触电阻，通过形成的TiSi2（二硅化钛）或其它难熔金属硅化物减少。二硅化钛消耗在第二多晶硅层的部分在P-N结的接触和在在Sametime消耗下面的第一多晶硅层的一小部分，检查做了高电阻的P-N结现在已不存在。以形成低电阻接触的方法被扩展以实现低泄漏多晶硅-TFT元件中。一个或多个LDD区域形成，以减少搜索的“OFF”状态的晶体管器件的漏电流的量。该装置的源极/漏极区（S）被植入随后蚀刻形成所述源/漏区上方间隔一第一掺杂物类型。然后，源/漏区注入有第二掺杂剂类型，以便没有LDD区形成的隔件的下面。在器件的栅极和源极/漏极的边界的电场分布在整个LDD区，在较低的峰值电场，并且因此较少器件泄漏电流引起的。

39. 发明公开

EP0565231A3 Method of fabricating a polysilicon thin film transistor 失效
标题翻译：制备多晶硅薄膜晶体管的方法
公开(公告)号：EP0565231A3
公开(公告)日：1996-11-20
申请号：EP93301646.1
申请日：1993-03-04
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Sundaresan, Ravishankar
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/66765 , H01L29/78624
摘要： A method is provided for forming a thin film transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A polysilicon gate electrode is formed over a portion of the integrated circuit. Agate oxide layer is formed over the gate electrode. A conformal polysilicon layer is formed over the gate oxide layer and a portion of the integrated circuit. The polysilicon layer is doped with an n-type dopant to form a channel region over the gate electrode. A screen oxide layer is formed over a portion of the polysilicon layer substantially over the gate electrode. The polysilicon layer not covered by the screen oxide layer is doped with a p - -type dopant to form a lightly doped drain region on each side of the channel region. A photoresist layer is formed over a portion of the screen oxide layer and one of the lightly doped drain regions. The polysilicon layer not covered by the photoresist layer is doped with a p + -type dopant. The photoresist layer is then removed. A conformal oxide layer is formed over the integrated circuit. The conformal oxide layer is then patterned and etched to form sidewall spacers on the sides of the screen oxide layer and the polysilicon layer adjacent to the screen oxide layer. The polysilicon layer not covered with the screen oxide layer or the sidewall oxide spacers is doped with a p + -type dopant. The screen oxide layer and the sidewall oxide spacers are then removed.
摘要翻译：提供一种用于形成半导体集成电路的薄膜晶体管的方法和根据该集成电路形成的集成电路。在集成电路的一部分上形成多晶硅栅电极。玛瑙氧化物层形成在栅电极上。在栅极氧化物层和集成电路的一部分上形成共形多晶硅层。多晶硅层掺杂有n型掺杂剂以在栅电极上形成沟道区。在多晶硅层的一部分上基本上在栅极上形成屏蔽氧化物层。未被屏蔽氧化物层覆盖的多晶硅层掺杂有p +型掺杂剂，以在沟道区域的每一侧上形成轻掺杂漏极区。在屏幕氧化物层的一部分和轻掺杂漏极区之一上形成光致抗蚀剂层。未被光致抗蚀剂层覆盖的多晶硅层掺杂有p +型掺杂剂。然后除去光致抗蚀剂层。在集成电路上形成保形氧化物层。然后对共形氧化物层进行图案化和蚀刻，以在屏幕氧化物层的侧面和与屏幕氧化物层相邻的多晶硅层形成侧壁间隔物。未被屏蔽氧化物层或侧壁氧化物间隔物覆盖的多晶硅层掺杂有p +型掺杂剂。然后去除屏幕氧化物层和侧壁氧化物间隔物。

40. 发明公开

EP0742682A2 Low-profile socketed integrated circuit packaging system 失效
标题翻译： IC封装采集系统与低调
公开(公告)号：EP0742682A2
公开(公告)日：1996-11-13
申请号：EP96302902.0
申请日：1996-04-24
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hundt, Michael J. , Chiu, Anthony M.
IPC分类号： H05K7/10
CPC分类号： H05K7/1069 , H01L23/4093 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： A socketed integrated circuit packaging system, including a packaged integrated circuit and a socket therefor, is disclosed. The integrated circuit package includes a device circuit board to which a thermally conductive slug is mounted; the underside of the device circuit board has a plurality of lands arranged in an array. The integrated circuit chip is mounted to the slug, through a hole in the device circuit board, and is wire-bonded to the device circuit board and thus to the lands on the underside. The socket is a molded frame, having a hole therethrough to receive the conductive slug of the integrated circuit package; the socket may also have its own thermally conductive slug disposed within the hole of the frame. The socket has spring contact members at locations matching the location of the lands on the device circuit board. The integrated circuit package may be inserted into the socket frame, held there by a metal or molded clip. A low profile, low cost, and high thermal conductivity package and socket combination, is thus produced.

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