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31. 发明授权

EP1012993B1 A RADIO FRONT-END CIRCUIT 失效
标题翻译： FUNKEINGANGSSCHALTUNG
公开(公告)号：EP1012993B1
公开(公告)日：2004-10-20
申请号：EP98900790.1
申请日：1998-01-07
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MATTISSON, Sven
IPC分类号： H04B1/26
CPC分类号： H04W52/028 , H04B1/26 , Y02D70/40
摘要： In a radio front-end circuit having at least two amplifier-mixer cascades, the amplifiers are switched on or off via the mixers. By switching between the amplifier-mixer cascades, the power consumption is lowered.

32. 发明授权

EP1095476B1 INTERFERENCE PREVENTION IN A RADIO COMMUNICATIONS SYSTEM 有权
标题翻译：防干扰在无线传输系统
公开(公告)号：EP1095476B1
公开(公告)日：2002-11-06
申请号：EP99932820.6
申请日：1999-07-05
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： BRISTOW, Robert Owen , MATTISSON, Sven
IPC分类号： H04B17/00 , H04B1/10 , H04B1/713
CPC分类号： H04W16/14 , H04B1/713
摘要： In a radio communications unit with several transceivers communicating in different frequency bands, a signal parameter of a selected channel is monitored in order to detect interference due to intermodulation products. The select channel is for example used by a long range radio communications link and the interfering channel on a short range radio link. Once the channel causing interference has been identified, transmissions on it are prevented.

33. 发明公开

EP1095476A1 INTERFERENCE PREVENTION IN A RADIO COMMUNICATIONS SYSTEM 有权
标题翻译：防干扰在无线传输系统
公开(公告)号：EP1095476A1
公开(公告)日：2001-05-02
申请号：EP99932820.6
申请日：1999-07-05
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： BRISTOW, Robert Owen , MATTISSON, Sven
IPC分类号： H04B17/00 , H04B1/10 , H04B1/713
CPC分类号： H04W16/14 , H04B1/713
摘要： In a radio communications unit with several transceivers communicating in different frequency bands, a signal parameter of a selected channel is monitored in order to detect interference due to intermodulation products. The select channel is for example used by a long range radio communications link and the interfering channel on a short range radio link. Once the channel causing interference has been identified, transmissions on it are prevented.

34. 发明公开

EP1066675A1 DEMOLUDATOR CIRCUITS 审中-公开
标题翻译： DEMODULATORSCHALTUNGEN
公开(公告)号：EP1066675A1
公开(公告)日：2001-01-10
申请号：EP99910368.2
申请日：1999-03-19
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： MATTISSON, Sven , HAARTSEN, Jacobus
IPC分类号： H03D3/00 , H04L27/14
CPC分类号： H03D3/005 , H04L27/152
摘要： A demoludator circuit for demoludating a frequency modulated input signal comprises filter means (10) and detector means (14) for receiving a frequency modulated input signal and for providing a demoludated output signal, tuning means (19) for tuning the frequency characterictics of the filter means and of the detector means, and DC offset estimator means (18) wich are operable to estim ate the DC offset of the demoludated output signal, and to produce an offset signal representing the estimated DC offset, and to provide the offset signal to the tuning means. The tuning means are operable to tune the frequency characteristics of the filter means and detector means in dependence upon the offset signal.

35. 发明公开

EP3342039A1 LOW POWER AND AREA BOOTSTRAPPED PASSIVE MIXER WITH SHARED CAPACITANCES 有权
公开(公告)号：EP3342039A1
公开(公告)日：2018-07-04
申请号：EP16757874.9
申请日：2016-08-25
申请人： Telefonaktiebolaget LM Ericsson (PUBL)
发明人： MASTANTUONO, Daniele , MATTISSON, Sven
IPC分类号： H03D7/14 , H03D7/16 , H04L25/08
CPC分类号： H03D7/1466 , H03D7/1441 , H03D7/1458 , H03D7/165
摘要： In a passive mixer, switches and a capacitance are shared between bootstrapped mixing transistors, reducing the number of components required as compared to prior art bootstrap designs. Shared bootstrap circuits operate in an interleaved fashion between I and Q mixer circuits, at twice the LO frequency. That is, the shared bootstrap circuits in each I mixer circuit charge their capacitors in a first half-period of a clock, and connect the shared capacitor to the gate of an enabled mixing transistor in the second half-period. The shared bootstrap circuits in the Q mixer circuit charge their capacitors in the second half-period, and connect the shared capacitor to the gate of an enabled mixing transistor in the first half-period. One of two mixing transistors connected to each shared bootstrap circuit is alternately enabled during the clock signal half-periods that the shared bootstrap circuit is not charging its capacitor.

36. 发明公开

EP3278459A1 RECEIVING A PLURALITY OF RADIO FREQUENCY BANDS 有权
标题翻译：接收多个无线电频带
公开(公告)号：EP3278459A1
公开(公告)日：2018-02-07
申请号：EP15714786.9
申请日：2015-03-31
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MASTANTUONO, Daniele , MATTISSON, Sven , STRANDBERG, Roland , SUNDSTRÖM, Lars
IPC分类号： H04B1/00 , H03F1/26
摘要： A radio frequency receiver comprises a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

37. 发明公开

EP3272007A1 AMPLIFIER ADAPTED FOR NOISE SUPPRESSION 有权
标题翻译：放大器适合噪音抑制
公开(公告)号：EP3272007A1
公开(公告)日：2018-01-24
申请号：EP15715174.7
申请日：2015-03-16
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MASTANTUONO, Daniele , MATTISSON, Sven
IPC分类号： H03F1/26
CPC分类号： H03F1/26 , H03F1/0205 , H03F1/3211 , H03F1/483 , H03F3/193 , H03F3/45179 , H03F3/607 , H03F2200/06 , H03F2200/294 , H03F2200/333 , H03F2200/451 , H03F2203/45306 , H03F2203/45318 , H04B1/12
摘要： An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (MCG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (MCG1) further having a first source (112) coupled to the first input (102). A second transistor (MCS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (MCS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (MCS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (MCS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (MCG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (MCG2) further having a fourth source (132) coupled to the second input (104). A first load (ZL1) is coupled between the first output (106) and a second voltage rail (136). A second load (ZL2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (MCG1) is substantially equal to transconductance of the fourth transistor (MCG2), within ±5%, and transconductance of the second transistor (MCS1) is substantially equal to transconductance of the third transistor (MCS2), within ±5%.

38. 发明公开

EP3254374A1 HIGH BANDWIDTH AMPLIFIER 有权
标题翻译：高带宽放大器
公开(公告)号：EP3254374A1
公开(公告)日：2017-12-13
申请号：EP15709101.8
申请日：2015-02-04
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MASTANTUONO, Daniele , MATTISSON, Sven
IPC分类号： H03F1/22 , H03F1/08 , H03F3/193
CPC分类号： H03F1/42 , H03F1/08 , H03F1/223 , H03F3/19 , H03F3/193 , H03F3/605 , H03F3/68 , H03F2200/36 , H03F2200/451
摘要： An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor (M4) coupled to the first output (22), a second terminal (T42) of the fourth transistor (M4) coupled to a fourth voltage rail (24), and a gate (G4) of the fourth transistor (M4) coupled to the second terminal (T32) of the third transistor (M3); and a first capacitive element (C1) coupled between the second terminal (T32) of the third transistor (M3) and the first output (22).

39. 发明公开

EP3228005A1 AN ATTENUATOR 有权
标题翻译：衰减器
公开(公告)号：EP3228005A1
公开(公告)日：2017-10-11
申请号：EP14809352.9
申请日：2014-12-03
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MU, Fenghao , MATTISSON, Sven
IPC分类号： H03H7/25 , H03G1/00
CPC分类号： H03H7/25 , H03G1/0088
摘要： An attenuator (100) for attenuating a signal is disclosed. The attenuator (100) comprises a differential input port (Inp; Inn) with a positive input node (Inp) and a negative input node (Inn) to receive the signal; and a differential output port (Outp; Outn) with a positive output node (Outp) and a negative output node (Outn) to output the attenuated signal. The attenuator (100) further comprises a first switched resistor network (102) connected between the positive input node (Inp) and the positive output node (Outp); and a second switched resistor network (104) connected between the negative input node (Inn) and the negative output node (Outn). Further a pair of compensation paths is connected to the first and second switched resistor networks (102; 104) for cancellation their parasitic leakages, where a first compensation path (106) is connected between the positive input node (Inp) and the negative output node (Outn), and a second compensation path (108) is connected between the negative input node (Inn) and the positive output node (Outp). The attenuator (100) further comprises a control circuit (110) to generate control signals for controlling the first and second switched resistor networks (102; 104).
摘要翻译：公开了一种用于衰减信号的衰减器（100）。衰减器（100）包括具有正输入节点（Inp）和负输入节点（Inn）的差分输入端口（Inp; Inn）以接收信号; 和具有正输出节点（Outp）和负输出节点（Outn）的差分输出端口（Outp; Outn）以输出衰减信号。衰减器（100）还包括连接在正输入节点（Inp）和正输出节点（Outp）之间的第一开关电阻网络（102）; 和连接在负输入节点（Inn）和负输出节点（Outn）之间的第二切换电阻器网络（104）。此外，一对补偿路径连接到第一和第二开关电阻网络（102; 104）以消除它们的寄生泄漏，其中第一补偿路径（106）连接在正输入节点（Inp）和负输出节点（Outn），并且第二补偿路径（108）连接在负输入节点（Inn）和正输出节点（Outp）之间。衰减器（100）还包括控制电路（110），以产生用于控制第一和第二开关电阻网络（102; 104）的控制信号。

40. 发明授权

EP2947769B1 LOW-NOISE AMPLIFIER 有权
标题翻译： RAUSCHARMERVERSTÄRKER
公开(公告)号：EP2947769B1
公开(公告)日：2017-04-05
申请号：EP15171109.0
申请日：2012-02-01
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： MATTISSON, Sven , ANDERSSON, Stefan
IPC分类号： H03F1/26 , H03F3/195 , H03F1/30 , H03F1/34 , H03F1/56 , H03F3/185
CPC分类号： H03F1/301 , H03F1/26 , H03F1/342 , H03F1/565 , H03F3/185 , H03F3/195 , H03F2200/129 , H03F2200/294 , H03F2200/384 , H03F2200/75
摘要： A common source or common emitter LNA circuit (30) for amplifying signals at an operating frequency f in a receiver circuit (10) is disclosed. The LNA circuit (30) comprises an input transistor (50) arranged to, in operation, be biased to have a transconductance g m at the operating frequency f, and having a first terminal (52), which is a gate or base terminal, operatively connected to an input terminal (32) of the LNA circuit (30). The LNA circuit (30) further comprises a shunt-feedback capacitor (60) operatively connected between the first terminal (52) of the input transistor (50) and a second terminal (54), which is a drain or collector terminal, of the input transistor (50). Furthermore, the LNA circuit (30) comprises an output capacitor (65) operatively connected between the second terminal (54) of the input transistor (50) and an output terminal (34) of the LNA circuit. The output capacitor (65) has a capacitance value C L
摘要翻译：公开了一种用于在接收机电路（10）中以工作频率f放大信号的公共源极或公共发射极LNA电路（30）。 LNA电路（30）包括输入晶体管（50），其被布置成在操作中被偏置为具有在工作频率f处的跨导gm，并且具有作为栅极或基极端子的第一端子（52），其可操作地连接到LNA电路（30）的输入端子（32）。 LNA电路（30）还包括可操作地连接在输入晶体管（50）的第一端子（52）和作为漏极或集电极端子的第二端子（54）之间的分流反馈电容器（60）输入晶体管（50）。此外，LNA电路（30）包括可操作地连接在输入晶体管（50）的第二端子（54）和LNA电路的输出端子（34）之间的输出电容器（65）。输出电容器65具有电容值C L

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